On Nov 8, 2013, at 4:51 PM, Scott Wood wrote:
On Wed, 2013-10-30 at 19:07 -0700, York Sun wrote:
Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM.
Signed-off-by: York Sun yorksun@freescale.com
drivers/ddr/fsl/Makefile | 1 + drivers/ddr/fsl/arm_ddr_gen3.c | 213 ++++++++++++++++++++++++++++++++++++++++ drivers/ddr/fsl/main.c | 12 ++- drivers/ddr/fsl/util.c | 4 + 4 files changed, 227 insertions(+), 3 deletions(-) create mode 100644 drivers/ddr/fsl/arm_ddr_gen3.c
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index cbbd178..381ec6c 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN1) += mpc85xx_ddr_gen1.o COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN2) += mpc85xx_ddr_gen2.o COBJS-$(CONFIG_SYS_FSL_DDR_PPC_GEN3) += mpc85xx_ddr_gen3.o COBJS-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o +COBJS-$(CONFIG_SYS_FSL_DDR_ARM_GEN3) += arm_ddr_gen3.o COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
I'm confused -- is this hardware the same across CPU families or not?
The algorithm is the same for all DDR controllers. The final part of writing to registers is slightly different. For example, 85xx SoCs have LAWs, ARM parts don't. 85xx driver needs to deal with both DDR2 and DDR3, while ARM driver doesn't. I also don't want to carry some messy workarounds from 85xx to ARM driver. It's much cleaner to keep them separated. The final part is very small in size.
York