From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T102x integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/t102x.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 2393e316f8..c49fd21088 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,4 +49,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; };