Various commands to NAND flash results in the NAND flash becoming busy. For those commands the SoC should wait until the NAND indicates it is no longer busy before sending further commands. However, there is a delay between the time the SoC sends its last command and when the NAND flash sets its Ready/Busy Pin. This delay (tWB) must be respected or the SoC may falsely assume the flash is ready when in reality it just hasn't had enough time to indicate that it is busy.
Properly delaying by tWB is already done for nand_command/nand_command_lp in nand_base.c including the version of it in the Linux kernel. Therefore, this patch brings the handling of tWB delay inline to nand_base.c
Signed-off-by: Franklin S Cooper Jr fcooper@ti.com --- drivers/mtd/nand/am335x_spl_bch.c | 50 +++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index a8a7a66..fdf6728 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -49,6 +49,12 @@ static int nand_command(int block, int page, uint32_t offs,
if (cmd == NAND_CMD_RESET) { hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + + /* * Apply this short delay always to ensure that we do wait + * tWB in any case on any machine. + */ + ndelay(150); + while (!this->dev_ready(mtd)) ; return 0; @@ -78,23 +84,43 @@ static int nand_command(int block, int page, uint32_t offs,
hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- if (cmd == NAND_CMD_READ0) { - /* Latch in address */ - hwctrl(mtd, NAND_CMD_READSTART, - NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- /* - * Wait a while for the data to be ready - */ - while (!this->dev_ready(mtd)) - ; - } else if (cmd == NAND_CMD_RNDOUT) { + /* + * Program and erase have their own busy handlers status, sequential + * in and status need no delay. + */ + switch (cmd) { + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_RNDIN: + case NAND_CMD_STATUS: + return 0; + + case NAND_CMD_RNDOUT: + /* No ready / busy check necessary */ hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | - NAND_CTRL_CHANGE); + NAND_CTRL_CHANGE); + hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + return 0; + + case NAND_CMD_READ0: + /* Latch in address */ + hwctrl(mtd, NAND_CMD_READSTART, + NAND_CTRL_CLE | NAND_CTRL_CHANGE); hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); }
+ /* * Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. + */ + ndelay(150); + + while (!this->dev_ready(mtd)) + ; + return 0; }