On Mon, Jun 28, 2021 at 9:21 PM Chris Packham judge.packham@gmail.com wrote:
On Mon, Jun 28, 2021 at 7:20 PM Pali Rohár pali@kernel.org wrote:
On Monday 08 February 2021 21:24:09 Marek Behun wrote:
On Mon, 8 Feb 2021 20:14:26 +0000 Chris Packham Chris.Packham@alliedtelesis.co.nz wrote:
On 9/02/21 8:15 am, Marek Behun wrote:
This patch is needed on some Turris Omnia boards with Samsung DDR chips, otherwise DDR training fails in ~60% of cases.
Marvell send us this patch for testing, I have updated it a little.
Please test this on other A38x boards.
If it doesn't break anything on other boards, we can apply it and send it to mv-ddr-marvell upstream.
They gave us the same patch. I was hoping their SoC team would get it into mv-ddr-marvell (or even their vendor USP) but obviously they're still sitting on it. I know it improved matters for some of our boards but it didn't totally fix them we still had yield problems when we ramped up production.
There is a bug in the version they sent us:
in file ddr3_training_ip_engine.c there is a line added: if ((bit_bit_mask[sybphy_id] & (1 << bit_id)) == 1)
try chaning it to if (bit_bit_mask[sybphy_id] & (1 << bit_id))
This is fixed in the version I sent to mailing list
Hello Chris! Have you tried above modification if it fixes your issue?
I haven't tried Marek's patch specifically. What we saw seemed to be a yield issue rather than something that could be tested on just one board. I must have missed Marek's response to my comment. Given that he's identified at least one problem with Marvell's SPLIT_OUT_MIX patch it's probably worth me trying it out on an x530 board. If that's OK then I think U-Boot can take the patch (or even better mv-ddr-marvell apply it and U-Boot syncs).
With http://patchwork.ozlabs.org/project/uboot/patch/20210208191225.14645-1-marek... applied on top of v2021.07-rc4 the x530 hangs after the SPL. I haven't had time to look into why.