This board has not been converted to CONFIG_DM_BLK by the deadline. Remove it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/mach-imx/mx6/Kconfig | 1 - board/ccv/xpress/Kconfig | 12 -- board/ccv/xpress/MAINTAINERS | 7 - board/ccv/xpress/Makefile | 6 - board/ccv/xpress/imximage.cfg | 175 ------------------ board/ccv/xpress/spl.c | 117 ------------ board/ccv/xpress/xpress.c | 336 ---------------------------------- configs/xpress_defconfig | 32 ---- configs/xpress_spl_defconfig | 42 ----- include/configs/xpress.h | 135 -------------- 10 files changed, 863 deletions(-) delete mode 100644 board/ccv/xpress/Kconfig delete mode 100644 board/ccv/xpress/MAINTAINERS delete mode 100644 board/ccv/xpress/Makefile delete mode 100644 board/ccv/xpress/imximage.cfg delete mode 100644 board/ccv/xpress/spl.c delete mode 100644 board/ccv/xpress/xpress.c delete mode 100644 configs/xpress_defconfig delete mode 100644 configs/xpress_spl_defconfig delete mode 100644 include/configs/xpress.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 194e8d855fc..3f0d27b76dd 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -529,7 +529,6 @@ source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" source "board/boundary/nitrogen6x/Kconfig" source "board/bticino/mamoj/Kconfig" -source "board/ccv/xpress/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" source "board/dhelectronics/dh_imx6/Kconfig" diff --git a/board/ccv/xpress/Kconfig b/board/ccv/xpress/Kconfig deleted file mode 100644 index 9157013c306..00000000000 --- a/board/ccv/xpress/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_XPRESS - -config SYS_BOARD - default "xpress" - -config SYS_VENDOR - default "ccv" - -config SYS_CONFIG_NAME - default "xpress" - -endif diff --git a/board/ccv/xpress/MAINTAINERS b/board/ccv/xpress/MAINTAINERS deleted file mode 100644 index e242bfb2065..00000000000 --- a/board/ccv/xpress/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -CCV XPRESS BOARD -M: Stefan Roese sr@denx.de -S: Maintained -F: board/ccv/xpress/ -F: include/configs/xpress.h -F: configs/xpress_defconfig -F: configs/xpress_spl_defconfig diff --git a/board/ccv/xpress/Makefile b/board/ccv/xpress/Makefile deleted file mode 100644 index b750b6ae498..00000000000 --- a/board/ccv/xpress/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2015-2016 Stefan Roese sr@denx.de - -obj-y := xpress.o -obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg deleted file mode 100644 index be7e391ddbe..00000000000 --- a/board/ccv/xpress/imximage.cfg +++ /dev/null @@ -1,175 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Stefan Roese sr@denx.de - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * sd, nand - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include <config.h> - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff -DATA 4 0x020c4084 0xffffffff - -/* ddr io type */ -DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ -DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ - -/* clock */ -DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ - -/* control and address */ -DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ -DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ -DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ -DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ -DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be - configured using Group Control Register: - IOMUXC_SW_PAD_CTL_GRP_CTLDS */ -DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ -DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ -DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ - -/* data strobes */ -DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ -DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ -DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ - -/* data */ -DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ -DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ -DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ -DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ -DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ - -/* - * DDR Controller Registers - * - * Manufacturer: IM - * Device Part Number: IME1G16D3EEBG-15EI - * Clock Freq.: 400MHz - * Density per CS in Gb: 1 - * Chip Selects used: 1 - * Number of Banks: 8 - * Row address: 13 - * Column address: 10 - * Data bus width 16 - */ -DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit - during MMDC set up */ - -/* - * Calibration setup - */ -DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & - periodic HW ZQ calibration. */ - -/* - * For target board, may need to run write leveling calibration to fine tune - * these settings. - */ -DATA 4 0x021b080c 0x00000000 - -/* Read DQS Gating calibration */ -DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */ - -/* Read calibration */ -DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */ - -/* Write calibration */ -DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */ - -/* - * read data bit delay: (3 is the reccommended default value, although out of - * reset value is 0) - */ -DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */ -DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */ -DATA 4 0x021b082c 0xF3333333 -DATA 4 0x021b0830 0xF3333333 - -DATA 4 0x021b08c0 0x00921012 - -/* Clock Fine Tuning */ -DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */ - -/* Complete calibration by forced measurement: */ -DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */ -/* - * Calibration setup end - */ - -/* MMDC init: */ -DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */ -DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */ -DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */ -DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */ -DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */ - -/* - * MDMISC: RALAT kept to the high level of 5. - * MDMISC: consider reducing RALAT if your 528MHz board design allow that. - * Lower RALAT benefits: - * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT - * to 3 - * b. Small performence improvment - */ -DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */ - -DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit - during MMDC set up */ - -DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */ -DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */ -DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */ -DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */ - -/* Mode register writes */ -DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */ -DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */ -DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */ -DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */ -DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to - device on CS0 */ - -DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ -DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */ -DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */ -DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will - enter automatically to self-refresh while the - number of idle cycle reached. */ -DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially - the configuration bit as initialization is - complete) */ diff --git a/board/ccv/xpress/spl.c b/board/ccv/xpress/spl.c deleted file mode 100644 index 90f655ab2e7..00000000000 --- a/board/ccv/xpress/spl.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SPL specific code for CCV xPress - * - * Copyright (C) 2015-2016 Stefan Roese sr@denx.de - */ - -#include <common.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch/mx6-ddr.h> -#include <asm/arch/crm_regs.h> - -/* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */ - -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; - -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000030, - .dram_odt1 = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000008, - .dram_sdqs0 = 0x00000038, - .dram_sdqs1 = 0x00000030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0x4164015C, - .p0_mprddlctl = 0x40404446, - .p0_mpwrdlctl = 0x40405A52, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* Setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* Setup iomux and i2c */ - board_early_init_f(); - - /* Setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); -} diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c deleted file mode 100644 index dcf5e1448f6..00000000000 --- a/board/ccv/xpress/xpress.c +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015-2016 Stefan Roese sr@denx.de - */ - -#include <asm/arch/clock.h> -#include <asm/arch/iomux.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6ul_pins.h> -#include <asm/arch/mx6-pins.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/io.h> -#include <common.h> -#include <fsl_esdhc.h> -#include <i2c.h> -#include <miiphy.h> -#include <mmc.h> -#include <netdev.h> -#include <usb.h> -#include <usb/ehci-ci.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_FAST) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, - .gp = IMX_GPIO_NR(1, 2), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3), - }, -}; - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; - -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC, - .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC, - .gp = IMX_GPIO_NR(1, 20), - }, - .sda = { - .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC, - .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC, - .gp = IMX_GPIO_NR(1, 21), - }, -}; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart5_pads[] = { - MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart7_pads[] = { - MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart8_pads[] = { - MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); - imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); - imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads)); - imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads)); -} - -/* eMMC on USDHC2 */ -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - /* - * RST_B - */ - MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg = { - .esdhc_base = USDHC2_BASE_ADDR, - .max_bus_width = 8, -}; - -#define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9) - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eMMC is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg); -} - -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - /* OTG1 */ - MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), - /* OTG2 */ - MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); -} - -int board_usb_phy_mode(int port) -{ - if (port == 1) - return USB_INIT_HOST; - else - return usb_phy_mode(port); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 1) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - /* Set Power polarity */ - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} - -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), - MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - - /* ENET1 reset */ - MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* ENET1 interrupt */ - MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17) - -int board_eth_init(bd_t *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - - /* Reset LAN8742 PHY */ - ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); - if (!ret) - gpio_direction_output(ENET_PHY_RESET_GPIO , 0); - mdelay(10); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); - mdelay(10); - - return cpu_eth_init(bis); -} - -static int setup_fec(int fec_id) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - /* - * Use 50M anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); - if (ret) - return ret; - - enable_enet_clk(1); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); - - setup_fec(CONFIG_FEC_ENET_DEV); - - setup_usb(); - - return 0; -} - -static const struct boot_mode board_boot_modes[] = { - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)}, - { NULL, 0 }, -}; - -int board_late_init(void) -{ - add_board_boot_modes(board_boot_modes); - env_set("board_name", "xpress"); - - return 0; -} - -int checkboard(void) -{ - puts("Board: CCV-EVA xPress\n"); - - return 0; -} diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig deleted file mode 100644 index caf0f6165aa..00000000000 --- a/configs/xpress_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_TARGET_XPRESS=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig deleted file mode 100644 index 7eefa92fc51..00000000000 --- a/configs/xpress_spl_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_XPRESS=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_ESDHC=y -CONFIG_PHYLIB=y -CONFIG_MII=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/xpress.h b/include/configs/xpress.h deleted file mode 100644 index 08e0ca0c8f1..00000000000 --- a/include/configs/xpress.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Stefan Roese sr@denx.de - * - * Configuration settings for the CCV xPress board - */ -#ifndef __XPRESS_CONFIG_H -#define __XPRESS_CONFIG_H - -#include "mx6_common.h" -#include <asm/mach-imx/gpio.h> - -/* SPL options */ -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (128 << 20) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment is in stored in the eMMC boot partition */ -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */ - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_FEC_MXC -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_PHY_SMSC - -#define CONFIG_IMX_THERMAL - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_UBOOT_SECTOR_START 0x2 -#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc6\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "uboot=ccv/u-boot.imx\0" \ - "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev 0 1;" \ - "setexpr blkc ${filesize} / 0x200;" \ - "setexpr blkc ${blkc} + 1;" \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc};" \ - "fi;" \ - "fi; fi;" \ - "setenv filesize; setenv blkc\0" \ - "update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0" - -#endif /* __XPRESS_CONFIG_H */