On 06/07/2016 02:28 AM, Yunhui Cui wrote:
From: Yunhui Cui yunhui.cui@nxp.com
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by: Yunhui Cui yunhui.cui@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 +++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 2 files changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d939900..1ac1067 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -639,6 +639,10 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif +#ifdef CONFIG_LS2080A
- u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
- u32 pmu_val;
+#endif #ifdef COUNTER_FREQUENCY_REAL unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -653,6 +657,17 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif
+#ifdef CONFIG_LS2080A +/*
- In certain Layerscape SoCs, the clock for each core's
- has an enable bit in the PMU Physical Core Time Base Enable
- Register (PCTBENR), which allows the watchdog to operate.
- */
+pmu_val = in_le32(pctbenr); +pmu_val |= 0xff; +out_le32(pctbenr, pmu_val); +#endif
You could use setbits_le32() instead of three lines. Also inappropriate indentation.
York