Hi Simon,
On Mon, Nov 25, 2019 at 12:12 PM Simon Glass sjg@chromium.org wrote:
Add a GPIO driver which uses the pinctrl driver to access the pad information. This driver relies on the GPIO nodes being subnodes to the pinctrl device.
Signed-off-by: Simon Glass sjg@chromium.org
Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None
.../gpio/intel,apl-gpio.txt | 55 ++++++ drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/intel_gpio.c | 161 ++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt create mode 100644 drivers/gpio/intel_gpio.c
diff --git a/doc/device-tree-bindings/gpio/intel,apl-gpio.txt b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt new file mode 100644 index 0000000000..e34e7c3501 --- /dev/null +++ b/doc/device-tree-bindings/gpio/intel,apl-gpio.txt @@ -0,0 +1,55 @@ +* Intel Apollo Lake GPIO controller
nits: remove the *
+The Apollo Lake (APL) GPIO controller is used to control GPIO functions of +the pins.
+Required properties: +- compatible: "intel,apl-gpio" +- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
- nodes should be the following with values derived from the SoC user manual.
<[phandle of the gpio controller node][pin number within the gpio controller][flags]>- Values for gpio specifier:
- Pin number: is a GPIO pin number between 0 and 244
- Flags: GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW
+- gpio-controller: Specifies that the node is a gpio controller.
+Example:
+... +{
p2sb: p2sb@d,0 {reg = <0x02006810 0 0 0 0>;compatible = "intel,apl-p2sb";early-regs = <IOMAP_P2SB_BAR 0x100000>;n {
Need a more descriptive name
compatible = "intel,apl-pinctrl";intel,p2sb-port-id = <PID_GPIO_N>;gpio_n: gpio-n {compatible = "intel,apl-gpio";gpio-controller;#gpio-cells = <2>;};};};i2c_2: i2c2@16,2 {compatible = "intel,apl-i2c", "snps,designware-i2c-pci";reg = <0x0200b210 0 0 0 0>;#address-cells = <1>;#size-cells = <0>;clock-frequency = <400000>;tpm@50 {reg = <0x50>;compatible = "google,cr50";u-boot,i2c-offset-len = <0>;ready-gpio = <&gpio_n GPIO_28 GPIO_ACTIVE_LOW>;};};+}; +... diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 447cf04578..1de6f5225e 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -104,6 +104,15 @@ config INTEL_BROADWELL_GPIO driver from the common Intel ICH6 driver. It supports a total of 95 GPIOs which can be configured from the device tree.
+config INTEL_GPIO
bool "Intel generic GPIO driver"depends on DM_GPIOhelpSay yes here to select Intel generic GPIO driver. This controllersupports recent chips (e.g. Apollo Lake). It permits basic GPIOcontrol including setting pins to input/output. It makes use of itsparent pinctrl driver to actually effect changes.config INTEL_ICH6_GPIO bool "Intel ICH6 compatible legacy GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3612e66786..449046b64c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o +obj-$(CONFIG_INTEL_GPIO) += intel_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c new file mode 100644 index 0000000000..eeff95de7b --- /dev/null +++ b/drivers/gpio/intel_gpio.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright 2019 Google LLC
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <p2sb.h> +#include <pch.h> +#include <pci.h> +#include <syscon.h> +#include <asm/cpu.h> +#include <asm/gpio.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_pinctrl_defs.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/arch/gpio.h> +#include <dt-bindings/gpio/x86-gpio.h>
+static int intel_gpio_direction_input(struct udevice *dev, uint offset) +{
struct udevice *pinctrl = dev_get_parent(dev);uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);pcr_clrsetbits32(pinctrl, config_offset,PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |PAD_CFG0_RX_DISABLE,PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);return 0;+}
+static int intel_gpio_direction_output(struct udevice *dev, uint offset,
int value)+{
struct udevice *pinctrl = dev_get_parent(dev);uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);pcr_clrsetbits32(dev, config_offset,PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |PAD_CFG0_TX_DISABLE,PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |(value ? PAD_CFG0_TX_STATE : 0));return 0;+}
+static int intel_gpio_get_value(struct udevice *dev, uint offset) +{
struct udevice *pinctrl = dev_get_parent(dev);uint mode, rx_tx;u32 reg;reg = intel_pinctrl_get_config_reg(pinctrl, offset);mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;if (!mode) {rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);if (rx_tx == PAD_CFG0_TX_DISABLE)return mode & PAD_CFG0_RX_STATE_BIT ? 1 : 0;else if (rx_tx == PAD_CFG0_RX_DISABLE)return mode & PAD_CFG0_TX_STATE_BIT ? 1 : 0;}return 0;+}
+static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value) +{
struct udevice *pinctrl = dev_get_parent(dev);uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);pcr_clrsetbits32(dev, config_offset, PAD_CFG0_TX_STATE,value ? PAD_CFG0_TX_STATE : 0);return 0;+}
+static int intel_gpio_get_function(struct udevice *dev, uint offset) +{
struct udevice *pinctrl = dev_get_parent(dev);uint mode, rx_tx;u32 reg;reg = intel_pinctrl_get_config_reg(pinctrl, offset);mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;if (!mode) {rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);if (rx_tx == PAD_CFG0_TX_DISABLE)return GPIOF_INPUT;else if (rx_tx == PAD_CFG0_RX_DISABLE)return GPIOF_OUTPUT;}return GPIOF_FUNC;+}
+static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
struct ofnode_phandle_args *args)+{
struct udevice *pinctrl, *dev;int gpio, ret;/** GPIO numbers are global in the device tree so it doesn't matter* which hone is used
What is hone?
*/gpio = args->args[0];ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);if (ret)return log_msg_ret("bad", ret);device_find_first_child(pinctrl, &dev);if (!dev)return log_msg_ret("no child", -ENOENT);desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;desc->dev = dev;return 0;+}
+static int intel_gpio_probe(struct udevice *dev) +{
return 0;+}
+static int intel_gpio_ofdata_to_platdata(struct udevice *dev) +{
struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);const struct pad_community *comm = pinctrl_priv->comm;upriv->gpio_count = comm->last_pad - comm->first_pad + 1;upriv->bank_name = dev->name;return 0;+}
+static const struct dm_gpio_ops gpio_intel_ops = {
.direction_input = intel_gpio_direction_input,.direction_output = intel_gpio_direction_output,.get_value = intel_gpio_get_value,.set_value = intel_gpio_set_value,.get_function = intel_gpio_get_function,.xlate = intel_gpio_xlate,+};
+static const struct udevice_id intel_intel_gpio_ids[] = {
{ .compatible = "intel,apl-gpio" },
If this is a generic Intel GPIO driver, probably we need a generic compatible string like "intel,gpio", and make use of the driver data for different SoC variants.
{ }+};
+U_BOOT_DRIVER(gpio_intel) = {
.name = "gpio_intel",.id = UCLASS_GPIO,.of_match = intel_intel_gpio_ids,.ops = &gpio_intel_ops,.ofdata_to_platdata = intel_gpio_ofdata_to_platdata,.probe = intel_gpio_probe,+};
Regards, Bin