On Mon, Nov 22, 2021 at 11:16:22AM +0000, Eugen.Hristev@microchip.com wrote:
On 11/8/21 5:07 PM, Chris Morgan wrote:
From: Chris Morgan macromorgan@hotmail.com
On my NTC CHIP whenever I do a cold boot any attached DIPs cannot be found. Rebooting on the other hand appears to fix the issue. I found that if I modified the timing slightly (but still within spec) the w1 identification on cold boot became far more reliable.
Signed-off-by: Chris Morgan macromorgan@hotmail.com
drivers/w1/w1-gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c index 9346f810ce..5565de2a92 100644 --- a/drivers/w1/w1-gpio.c +++ b/drivers/w1/w1-gpio.c @@ -22,8 +22,8 @@ #define W1_TIMING_E 9 #define W1_TIMING_F 55 #define W1_TIMING_G 0 -#define W1_TIMING_H 480 -#define W1_TIMING_I 70 +#define W1_TIMING_H 600 +#define W1_TIMING_I 100 #define W1_TIMING_J 410
struct w1_gpio_pdata {
2.30.2
Hi Chris,
I tested your patch on my board sama5d2_xplained, and it works. Thus, you can add my Tested-by: Eugen Hristev eugen.hristev@microchip.com
However, I disagree with the changes you did in timings. What I found was that timing 'H' could go up to 640 , but timing 'I' to a maximum of 75 or so. [1]
I am thinking maybe you could also check your udelays with a scope on the 1wire line ? Because your problem might be in fact in some other part , like udelays not properly aligned/synchronized/accurate at cold boot time, depending on the source of clock you are using.
I lack a scope, but will extensively test 640 and 75 as the new timings. Would that be acceptable?
Thank you.
Eugen
[1] https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.maximin...