This actually reverts the following 2 commits:
commit 427911001809 ("x86: Set up the MTRR for SDRAM") commit d46c0932a9d4 ("x86: fsp: Adjust calculations for MTRR range and DRAM top")
There are several outstanding issues as to why:
* For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8ad9aeedac..928c5225cd 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -11,7 +11,6 @@ #include <asm/e820.h> #include <asm/global_data.h> #include <asm/mrccache.h> -#include <asm/mtrr.h> #include <asm/post.h> #include <dm/ofnode.h>
@@ -42,10 +41,8 @@ int fsp_scan_for_ram_size(void)
int dram_init_banksize(void) { - efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID; const struct hob_header *hdr; struct hob_res_desc *res_desc; - phys_addr_t mtrr_top; phys_addr_t low_end; uint bank;
@@ -53,47 +50,35 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = gd->ram_size;
- mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); return 0; }
- low_end = 0; /* top of low memory usable by U-Boot */ - mtrr_top = 0; /* top of low memory (even if reserved) */ + low_end = 0; for (bank = 1, hdr = gd->arch.hob_list; bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); hdr = get_next_hob(hdr)) { if (hdr->type != HOB_TYPE_RES_DESC) continue; res_desc = (struct hob_res_desc *)hdr; - if (!guidcmp(&res_desc->owner, &fsp)) - low_end = res_desc->phys_start; if (res_desc->type != RES_SYS_MEM && res_desc->type != RES_MEM_RESERVED) continue; if (res_desc->phys_start < (1ULL << 32)) { - mtrr_top = max(mtrr_top, - res_desc->phys_start + res_desc->len); - } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; - mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, - res_desc->len); - log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + low_end = max(low_end, + res_desc->phys_start + res_desc->len); + continue; } + + gd->bd->bi_dram[bank].start = res_desc->phys_start; + gd->bd->bi_dram[bank].size = res_desc->len; + log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, + gd->bd->bi_dram[bank].size); }
/* Add the memory below 4GB */ gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = low_end;
- /* - * Set up an MTRR to the top of low, reserved memory. This is necessary - * for graphics to run at full speed in U-Boot. - */ - mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); - return 0; }
@@ -166,7 +151,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list); ho->arch.hob_list = gd->arch.hob_list;
return 0;