Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Only basic setup, not using the ECC features.
Signed-off-by: Ralph Siemsen ralph.siemsen@linaro.org ---
drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/cadence/Kconfig | 24 ++ drivers/ram/cadence/Makefile | 1 + drivers/ram/cadence/ddr_async.c | 295 +++++++++++++++++++++++ drivers/ram/cadence/ddr_ctrl.c | 414 ++++++++++++++++++++++++++++++++ drivers/ram/cadence/ddr_ctrl.h | 172 +++++++++++++ 7 files changed, 909 insertions(+) create mode 100644 drivers/ram/cadence/Kconfig create mode 100644 drivers/ram/cadence/Makefile create mode 100644 drivers/ram/cadence/ddr_async.c create mode 100644 drivers/ram/cadence/ddr_ctrl.c create mode 100644 drivers/ram/cadence/ddr_ctrl.h
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 86857c0627..ec0ab9ce8a 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -97,6 +97,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC.
source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/cadence/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 5a39611349..2a015cda48 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -22,3 +22,5 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o obj-$(CONFIG_RAM_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_OCTEON) += octeon/ + +obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig new file mode 100644 index 0000000000..864cadfd10 --- /dev/null +++ b/drivers/ram/cadence/Kconfig @@ -0,0 +1,24 @@ +if RAM || SPL_RAM + +config CADENCE_DDR_CTRL + bool "Enable Cadence DDR controller" + depends on DM + help + Enable support for Cadence DDR controller, as found on + the Renesas RZ/N1 SoC. This controller has a large number + of registers which need to be programmed, mostly using values + obtained from Denali SOMA files via a TCL script. + +if CADENCE_DDR_CTRL + +# TODO: convert this to devicetree option +config CADENCE_DDR_CTRL_ENABLE_ECC + bool "Enable ECC support" + +# TODO: conver this to devicetree option +config CADENCE_DDR_CTRL_8BIT_WIDTH + bool "Reduce data width from 16 to 8 bits" + +endif + +endif diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile new file mode 100644 index 0000000000..16c7fe8488 --- /dev/null +++ b/drivers/ram/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_async.o ddr_ctrl.o diff --git a/drivers/ram/cadence/ddr_async.c b/drivers/ram/cadence/ddr_async.c new file mode 100644 index 0000000000..1d6d3bdc79 --- /dev/null +++ b/drivers/ram/cadence/ddr_async.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * RZ/N1 DDR Controller initialisation + * + * The DDR Controller register values for a specific DDR device, mode and + * frequency are generated using a Cadence tool. + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <ram.h> +#include <asm/io.h> +#include <linux/delay.h> +#include "ddr_ctrl.h" + +void clk_rzn1_reset_state(struct clk *clk, int on); + +extern u32 ddr_00_87_async[]; +extern u32 ddr_350_374_async[]; + +DECLARE_GLOBAL_DATA_PTR; + +struct cadence_ddr_info { + struct udevice *dev; + void __iomem *ddrc; + void __iomem *phy; + struct clk clk_ddrc; + struct clk hclk_ddrc; +}; + +static inline u32 cadence_readl(void __iomem *addr, unsigned int offset) +{ + return readl(addr + offset); +} + +static inline void cadence_writel(void __iomem *addr, unsigned int offset, + u32 data) +{ + debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset, data); + writel(data, addr + offset); +} + +#define ddrc_readl(off) cadence_readl(priv->ddrc, off) +#define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val) + +#define phy_readl(off) cadence_readl(priv->phy, off) +#define phy_writel(val, off) cadence_writel(priv->phy, off, val) + +#define RZN1_DDR3_SINGLE_BANK 3 +#define RZN1_DDR3_DUAL_BANK 32 + +#define FUNCCTRL 0x00 +#define FUNCCTRL_MASKSDLOFS (0x18 << 16) +#define FUNCCTRL_DVDDQ_1_5V (1 << 8) +#define FUNCCTRL_RESET_N (1 << 0) +#define DLLCTRL 0x04 +#define DLLCTRL_ASDLLOCK (1 << 26) +#define DLLCTRL_MFSL_500MHz (2 << 1) +#define DLLCTRL_MDLLSTBY (1 << 0) +#define ZQCALCTRL 0x08 +#define ZQCALCTRL_ZQCALEND (1 << 30) +#define ZQCALCTRL_ZQCALRSTB (1 << 0) +#define ZQODTCTRL 0x0c +#define RDCTRL 0x10 +#define RDTMG 0x14 +#define FIFOINIT 0x18 +#define FIFOINIT_RDPTINITEXE (1 << 8) +#define FIFOINIT_WRPTINITEXE (1 << 0) +#define OUTCTRL 0x1c +#define OUTCTRL_ADCMDOE (1 << 0) +#define WLCTRL1 0x40 +#define WLCTRL1_WLSTR (1 << 24) +#define DQCALOFS1 0xe8 + +/* DDR PHY setup */ +void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type) +{ + u32 val; + + /* Disable DDR Controller clock and FlexWAY connection */ + clk_disable(&priv->hclk_ddrc); + clk_disable(&priv->clk_ddrc); + + clk_rzn1_reset_state(&priv->hclk_ddrc, 0); + clk_rzn1_reset_state(&priv->clk_ddrc, 0); + + /* Enable DDR Controller clock and FlexWAY connection */ + clk_enable(&priv->clk_ddrc); + clk_enable(&priv->hclk_ddrc); + + /* DDR PHY Soft reset assert */ + ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL); + + clk_rzn1_reset_state(&priv->hclk_ddrc, 1); + clk_rzn1_reset_state(&priv->clk_ddrc, 1); + + /* DDR PHY setup */ + phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL); + phy_writel(0x00000182, ZQCALCTRL); + if (ddr_type == RZN1_DDR3_DUAL_BANK) + phy_writel(0xAB330031, ZQODTCTRL); + else if (ddr_type == RZN1_DDR3_SINGLE_BANK) + phy_writel(0xAB320051, ZQODTCTRL); + else /* DDR2 */ + phy_writel(0xAB330071, ZQODTCTRL); + phy_writel(0xB545B544, RDCTRL); + phy_writel(0x000000B0, RDTMG); + phy_writel(0x020A0806, OUTCTRL); + if (ddr_type == RZN1_DDR3_DUAL_BANK) + phy_writel(0x80005556, WLCTRL1); + else + phy_writel(0x80005C5D, WLCTRL1); + phy_writel(0x00000101, FIFOINIT); + phy_writel(0x00004545, DQCALOFS1); + + /* Step 9 MDLL reset release */ + val = phy_readl(DLLCTRL); + val &= ~DLLCTRL_MDLLSTBY; + phy_writel(val, DLLCTRL); + + /* Step 12 Soft reset release */ + val = phy_readl(FUNCCTRL); + val |= FUNCCTRL_RESET_N; + phy_writel(val, FUNCCTRL); + + /* Step 13 FIFO pointer initialize */ + phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT); + + /* Step 14 Execute ZQ Calibration */ + val = phy_readl(ZQCALCTRL); + val |= ZQCALCTRL_ZQCALRSTB; + phy_writel(val, ZQCALCTRL); + + /* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */ + while (!(phy_readl(DLLCTRL) & DLLCTRL_ASDLLOCK)) + ; + while (!(phy_readl(ZQCALCTRL) & ZQCALCTRL_ZQCALEND)) + ; + + /* Step 16 Enable Address and Command output */ + val = phy_readl(OUTCTRL); + val |= OUTCTRL_ADCMDOE; + phy_writel(val, OUTCTRL); + + /* Step 17 Wait for 200us or more(from MRESETB=0) */ + udelay(200); +} + +void ddr_phy_enable_wl(struct cadence_ddr_info *priv) +{ + u32 val; + + /* Step 26 (Set Write Leveling) */ + val = phy_readl(WLCTRL1); + val |= WLCTRL1_WLSTR; + phy_writel(val, WLCTRL1); +} + +#define RZN1_DDR_BASE 0x4000D000 /* RZ/N1D only */ +#define RZN1_V_DDR_BASE 0x80000000 /* RZ/N1D only */ + +void rzn1_ddr3_single_bank(void *ddr_ctrl_base) +{ + /* CS0 */ + cdns_ddr_set_mr1(ddr_ctrl_base, 0, + MR1_ODT_IMPEDANCE_60_OHMS, + MR1_DRIVE_STRENGTH_40_OHMS); + cdns_ddr_set_mr2(ddr_ctrl_base, 0, + MR2_DYNAMIC_ODT_OFF, + MR2_SELF_REFRESH_TEMP_EXT); + + /* ODT_WR_MAP_CS0 = 1, ODT_RD_MAP_CS0 = 0 */ + cdns_ddr_set_odt_map(ddr_ctrl_base, 0, 0x0100); +} + +int rzn1_dram_init(struct cadence_ddr_info *priv) +{ + u32 ddr_start_addr = 0; + + ddr_phy_init(priv, RZN1_DDR3_SINGLE_BANK); + + /* + * Override DDR PHY Interface (DFI) related settings + * DFI is the internal interface between the DDR controller and the DDR PHY. + * These settings are specific to LCES2 and can't be known by the settings + * provided for each DDR model within the generated include. + */ + ddr_350_374_async[351 - 350] = 0x001e0000; + ddr_350_374_async[352 - 350] = 0x1e680000; + ddr_350_374_async[353 - 350] = 0x02000020; + ddr_350_374_async[354 - 350] = 0x02000200; + ddr_350_374_async[355 - 350] = 0x00000c30; + ddr_350_374_async[356 - 350] = 0x00009808; + ddr_350_374_async[357 - 350] = 0x020a0706; + ddr_350_374_async[372 - 350] = 0x01000000; + +#if 0 + /* + * On ES1.0 devices, the DDR start address that the DDR Controller sees + * is the physical address of the DDR. However, later devices changed it + * to be 0 in order to fix an issue with DDR out-of-range detection. + */ + if (sysctrl_readl(RZN1_SYSCTRL_REG_VERSION) == 0x10) + ddr_start_addr = RZN1_V_DDR_BASE; +#endif + + /* DDR Controller is always in ASYNC mode */ + cdns_ddr_ctrl_init((void *)RZN1_DDR_BASE, 1, + ddr_00_87_async, ddr_350_374_async, + ddr_start_addr, CONFIG_SYS_SDRAM_SIZE); + + rzn1_ddr3_single_bank((void *)RZN1_DDR_BASE); + cdns_ddr_set_diff_cs_delays((void *)RZN1_DDR_BASE, 2, 7, 2, 2); + cdns_ddr_set_same_cs_delays((void *)RZN1_DDR_BASE, 0, 7, 0, 0); + cdns_ddr_set_odt_times((void *)RZN1_DDR_BASE, 5, 6, 6, 0, 4); + cdns_ddr_ctrl_start((void *)RZN1_DDR_BASE); + + ddr_phy_enable_wl(priv); + + if (IS_ENABLED(CONFIG_CADENCE_DDR_CTRL_ENABLE_ECC)) { + /* + * Any read before a write will trigger an ECC un-correctable error, + * causing a data abort. However, this is also true for any read with a + * size less than the AXI bus width. So, the only sensible solution is + * to write to all of DDR now and take the hit... + */ + memset((void *)RZN1_V_DDR_BASE, 0xff, CONFIG_SYS_SDRAM_SIZE); + } + + return 0; +} + +static int cadence_ddr_get_info(struct udevice *udev, struct ram_info *info) +{ + info->base = 0; + info->size = gd->ram_size; + + return 0; +} + +static struct ram_ops cadence_ddr_ops = { + .get_info = cadence_ddr_get_info, +}; + +static int cadence_ddr_probe(struct udevice *dev) +{ + struct cadence_ddr_info *priv = dev_get_priv(dev); + int ret; + + priv->ddrc = dev_remap_addr_name(dev, "ddrc"); + if (!priv->ddrc) { + dev_err(dev, "No reg property for Cadence DDR CTRL\n"); + return -EINVAL; + } + + priv->phy = dev_remap_addr_name(dev, "phy"); + if (!priv->phy) { + dev_err(dev, "No reg property for Cadence DDR PHY\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "clk_ddrc", &priv->clk_ddrc); + if (ret) { + dev_err(dev, "No clock for Cadence DDR\n"); + return ret; + } + + ret = clk_get_by_name(dev, "hclk_ddrc", &priv->hclk_ddrc); + if (ret) { + dev_err(dev, "No HCLK for Cadence DDR\n"); + return ret; + } + + rzn1_dram_init(priv); + + return 0; +} + +static const struct udevice_id cadence_ddr_ids[] = { + { .compatible = "cadence,ddr-ctrl" }, + { } +}; + +U_BOOT_DRIVER(cadence_ddr) = { + .name = "cadence_ddr", + .id = UCLASS_RAM, + .of_match = cadence_ddr_ids, + .ops = &cadence_ddr_ops, + .probe = cadence_ddr_probe, + .priv_auto = sizeof(struct cadence_ddr_info), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c new file mode 100644 index 0000000000..833d5d9197 --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +/* + * The Cadence DDR Controller has a huge number of registers that principally + * cover two aspects, DDR specific timing information and AXI bus interfacing. + * Cadence's TCL script generates all of the register values for specific + * DDR devices operating at a specific frequency. The TCL script uses Denali + * SOMA files as inputs. The tool also generates the AXI bus register values as + * well, however this driver assumes that users will want to modifiy these to + * meet a specific application's needs. + * Therefore, this driver is passed two arrays containing register values for + * the DDR device specific information, and explicity sets the AXI registers. + * + * AXI bus interfacing: + * The controller has four AXI slaves connections, and each of these can be + * programmed to accept requests from specific AXI masters (using their IDs). + * The regions of DDR that can be accessed by each AXI slave can be set such + * as to isolate DDR used by one AXI master from another. Further, the maximum + * bandwidth allocated to each AXI slave can be set. + */ + +#include <common.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include "ddr_ctrl.h" + +/* avoid warning for real pr_debug in <linux/printk.h> */ +#ifdef pr_debug +#undef pr_debug +#endif + +#ifdef DEBUG + #define pr_debug(fmt, args...) printf(fmt, ##args) + #define pr_debug2(fmt, args...) printf(fmt, ##args) +#else + #define pr_debug(fmt, args...) + #define pr_debug2(fmt, args...) +#endif + +#define DDR_NR_AXI_PORTS 4 +#define DDR_NR_ENTRIES 16 + +#define DDR_START_REG (0) /* DENALI_CTL_00 */ +#define DDR_CS0_MR1_REG (32 * 4) /* DENALI_CTL_32 */ +#define DDR_CS0_MR2_REG (32 * 4 + 2) /* DENALI_CTL_32 */ +#define DDR_CS1_MR1_REG (34 * 4 + 2) /* DENALI_CTL_34 */ +#define DDR_CS1_MR2_REG (35 * 4) /* DENALI_CTL_35 */ +#define DDR_ECC_ENABLE_REG (36 * 4 + 2) /* DENALI_CTL_36 */ +#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2) /* DENALI_CTL_37 */ +#define DDR_HALF_DATAPATH_REG (54 * 4) /* DENALI_CTL_54 */ +#define DDR_INTERRUPT_STATUS (56 * 4) /* DENALI_CTL_56 */ +#define DDR_INTERRUPT_ACK (57 * 4) /* DENALI_CTL_57 */ +#define DDR_INTERRUPT_MASK (58 * 4) /* DENALI_CTL_58 */ +#define DDR_CS0_ODT_MAP_REG (62 * 4 + 2) /* DENALI_CTL_62 */ +#define DDR_CS1_ODT_MAP_REG (63 * 4) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTL_2CMD (63 * 4 + 2) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTH_WR (63 * 4 + 3) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTH_RD (64 * 4 + 0) /* DENALI_CTL_64 */ +#define DDR_ODT_EN (64 * 4 + 1) /* DENALI_CTL_64 */ +#define DDR_ODT_WR_TO_ODTH (64 * 4 + 2) /* DENALI_CTL_64 */ +#define DDR_ODT_RD_TO_ODTH (64 * 4 + 3) /* DENALI_CTL_64 */ +#define DDR_DIFF_CS_DELAY_REG (66 * 4) /* DENALI_CTL_66 */ +#define DDR_SAME_CS_DELAY_REG (67 * 4) /* DENALI_CTL_67 */ +#define DDR_RW_PRIORITY_REGS (87 * 4 + 2) /* DENALI_CTL_87 */ +#define DDR_RW_FIFO_TYPE_REGS (88 * 4) /* DENALI_CTL_88 */ +#define DDR_AXI_PORT_PROT_ENABLE_REG (90 * 4 + 3) /* DENALI_CTL_90 */ +#define DDR_ADDR_RANGE_REGS (91 * 4) /* DENALI_CTL_91 */ +#define DDR_RANGE_PROT_REGS (218 * 4 + 2) /* DENALI_CTL_218 */ +#define DDR_ARB_CMD_Q_THRESHOLD_REG (346 * 4 + 2) /* DENALI_CTL_346 */ +#define DDR_AXI_PORT_BANDWIDTH_REG (346 * 4 + 3) /* DENALI_CTL_346 */ +#define DDR_OPT_RMODW_REG (372 * 4 + 3) /* DENALI_CTL_372 */ + +static void ddrc_writeb(u8 val, void *p) +{ + pr_debug2("DDR: %p = 0x%02x\n", p, val); + writeb(val, p); +} + +static void ddrc_writew(u16 val, void *p) +{ + pr_debug2("DDR: %p = 0x%04x\n", p, val); + writew(val, p); +} + +static void ddrc_writel(u32 val, void *p) +{ + pr_debug2("DDR: %p = 0x%08x\n", p, val); + writel(val, p); +} + +void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength) +{ + void *reg; + u16 tmp; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_MR1_REG; + else + reg = (u8 *)base + DDR_CS1_MR1_REG; + + tmp = readw(reg); + + tmp &= ~MODE_REGISTER_MASK; + tmp |= MODE_REGISTER_MR1; + + tmp &= ~MR1_ODT_IMPEDANCE_MASK; + tmp |= odt_impedance; + + tmp &= ~MR1_DRIVE_STRENGTH_MASK; + tmp |= drive_strength; + + writew(tmp, reg); +} + +void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp) +{ + void *reg; + u16 tmp; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_MR2_REG; + else + reg = (u8 *)base + DDR_CS1_MR2_REG; + + tmp = readw(reg); + + tmp &= ~MODE_REGISTER_MASK; + tmp |= MODE_REGISTER_MR2; + + tmp &= ~MR2_DYNAMIC_ODT_MASK; + tmp |= dynamic_odt; + + tmp &= ~MR2_SELF_REFRESH_TEMP_MASK; + tmp |= self_refresh_temp; + + writew(tmp, reg); +} + +void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map) +{ + void *reg; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_ODT_MAP_REG; + else + reg = (u8 *)base + DDR_CS1_ODT_MAP_REG; + + writew(odt_map, reg); +} + +void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, + u8 WR_TO_ODTH, u8 RD_TO_ODTH) +{ + writeb(TODTL_2CMD, (u8 *)base + DDR_ODT_TODTL_2CMD); + writeb(TODTH_WR, (u8 *)base + DDR_ODT_TODTH_WR); + writeb(TODTH_RD, (u8 *)base + DDR_ODT_TODTH_RD); + writeb(1, (u8 *)base + DDR_ODT_EN); + writeb(WR_TO_ODTH, (u8 *)base + DDR_ODT_WR_TO_ODTH); + writeb(RD_TO_ODTH, (u8 *)base + DDR_ODT_RD_TO_ODTH); +} + +void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) +{ + u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r; + + writel(val, (u8 *)base + DDR_SAME_CS_DELAY_REG); +} + +void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) +{ + u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r; + + writel(val, (u8 *)base + DDR_DIFF_CS_DELAY_REG); +} + +void cdns_ddr_set_port_rw_priority(void *base, int port, + u8 read_pri, u8 write_pri) +{ + u8 *reg8 = (u8 *)base + DDR_RW_PRIORITY_REGS; + + reg8 += (port * 3); + pr_debug("%s port %d (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, reg8, (reg8 - (u8 *)base) / 4); + + ddrc_writeb(read_pri, reg8++); + ddrc_writeb(write_pri, reg8++); +} + +/* The DDR Controller has 16 entries. Each entry can specify an allowed address + * range (with 16KB resolution) for one of the 4 AXI slave ports. + */ +void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, + u32 addr_start, u32 size) +{ + u32 addr_end; + u32 *reg32 = (u32 *)((u8 *)base + DDR_ADDR_RANGE_REGS); + u32 tmp; + + reg32 += (port * DDR_NR_ENTRIES * 2); + reg32 += (entry * 2); + pr_debug("%s port %d, entry %d (reg32=%p, DENALI_CTL_%d)\n", + __func__, port, entry, reg32, ((u8 *)reg32 - (u8 *)base) / 4); + + /* These registers represent 16KB address blocks */ + addr_start /= SZ_16K; + size /= SZ_16K; + if (size) + addr_end = addr_start + size - 1; + else + addr_end = addr_start; + + ddrc_writel(addr_start, reg32++); + + /* + * end_addr: Ensure we only set the bottom 18-bits as DENALI_CTL_218 + * also contains the AXI0 range protection bits. + */ + tmp = readl(reg32); + tmp &= ~(BIT(18) - 1); + tmp |= addr_end; + ddrc_writel(tmp, reg32); +} + +void cdns_ddr_enable_addr_range(void *base, int entry, + u32 addr_start, u32 size) +{ + int axi; + + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) + cdns_ddr_enable_port_addr_range(base, axi, entry, + addr_start, size); +} + +void cdns_ddr_enable_port_prot(void *base, int port, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup) +{ + /* + * Technically, the offset here points to the byte before the start of + * the range protection registers. However, all entries consist of 8 + * bytes, except the first one (which is missing a padding byte) so we + * work around that subtlely. + */ + u8 *reg8 = (u8 *)base + DDR_RANGE_PROT_REGS; + + reg8 += (port * DDR_NR_ENTRIES * 8); + reg8 += (entry * 8); + pr_debug("%s port %d, entry %d (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, entry, reg8, (reg8 - (u8 *)base) / 4); + + if (port == 0 && entry == 0) + ddrc_writeb(range_protection_bits, reg8 + 1); + else + ddrc_writeb(range_protection_bits, reg8); + + ddrc_writew(range_RID_check_bits, reg8 + 2); + ddrc_writew(range_WID_check_bits, reg8 + 4); + ddrc_writeb(range_RID_check_bits_ID_lookup, reg8 + 6); + ddrc_writeb(range_WID_check_bits_ID_lookup, reg8 + 7); +} + +void cdns_ddr_enable_prot(void *base, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup) +{ + int axi; + + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) + cdns_ddr_enable_port_prot(base, axi, entry, + range_protection_bits, + range_RID_check_bits, + range_WID_check_bits, + range_RID_check_bits_ID_lookup, + range_WID_check_bits_ID_lookup); +} + +void cdns_ddr_set_port_bandwidth(void *base, int port, + u8 max_percent, u8 overflow_ok) +{ + u8 *reg8 = (u8 *)base + DDR_AXI_PORT_BANDWIDTH_REG; + + reg8 += (port * 3); + pr_debug("%s port %d, (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, reg8, (reg8 - (u8 *)base) / 4); + + ddrc_writeb(max_percent, reg8++); /* Maximum bandwidth percentage */ + ddrc_writeb(overflow_ok, reg8++); /* Bandwidth overflow allowed */ +} + +void cdns_ddr_ctrl_init(void *ddr_ctrl_basex, int async, + const u32 *reg0, const u32 *reg350, + u32 ddr_start_addr, u32 ddr_size) +{ + int i, axi, entry; + u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex; + u8 *base8 = (u8 *)ddr_ctrl_basex; + + pr_debug("%s\n", __func__); + ddrc_writel(*reg0, ddr_ctrl_base + 0); + /* 1 to 6 are read only */ + for (i = 7; i <= 26; i++) + ddrc_writel(*(reg0 + i), ddr_ctrl_base + i); + /* 27 to 29 are not changed */ + for (i = 30; i <= 87; i++) + ddrc_writel(*(reg0 + i), ddr_ctrl_base + i); + + /* Enable/disable ECC */ + if (IS_ENABLED(CONFIG_CADENCE_DDR_CTRL_ENABLE_ECC)) { + pr_debug("%s enabling ECC\n", __func__); + ddrc_writeb(1, base8 + DDR_ECC_ENABLE_REG); + } else { + ddrc_writeb(0, base8 + DDR_ECC_ENABLE_REG); + } + + /* ECC: Disable corruption for read/modify/write operations */ + ddrc_writeb(1, base8 + DDR_ECC_DISABLE_W_UC_ERR_REG); + + /* Set 8/16-bit data width using reduc bit (enable half datapath)*/ + if (IS_ENABLED(CONFIG_CADENCE_DDR_CTRL_8BIT_WIDTH)) { + pr_debug("%s using 8-bit data\n", __func__); + ddrc_writeb(1, base8 + DDR_HALF_DATAPATH_REG); + } else { + ddrc_writeb(0, base8 + DDR_HALF_DATAPATH_REG); + } + + /* Threshold for command queue */ + ddrc_writeb(4, base8 + DDR_ARB_CMD_Q_THRESHOLD_REG); + + /* AXI port protection => enable */ + ddrc_writeb(0x01, base8 + DDR_AXI_PORT_PROT_ENABLE_REG); + + /* Set port interface type, default port priority and bandwidths */ + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) { + /* port interface type: synchronous or asynchronous AXI clock */ + u8 *fifo_reg = base8 + DDR_RW_FIFO_TYPE_REGS + (axi * 3); + + if (async) + ddrc_writeb(0, fifo_reg); + else + ddrc_writeb(3, fifo_reg); + + /* R/W priorities */ + cdns_ddr_set_port_rw_priority(ddr_ctrl_base, axi, 2, 2); + + /* AXI bandwidth */ + cdns_ddr_set_port_bandwidth(ddr_ctrl_base, axi, 50, 1); + } + + /* + * The hardware requires that the valid address ranges must not overlap. + * So, we initialise all address ranges to be above the DDR, length 0. + */ + for (entry = 0; entry < DDR_NR_ENTRIES; entry++) + cdns_ddr_enable_addr_range(ddr_ctrl_base, entry, + ddr_start_addr + ddr_size, 0); + + for (i = 350; i <= 374; i++) + ddrc_writel(*(reg350 - 350 + i), ddr_ctrl_base + i); + + /* Disable optimised read-modify-write logic */ + ddrc_writeb(0, base8 + DDR_OPT_RMODW_REG); + + /* + * Disable all interrupts, we are not handling them. + * For detail of the interrupt mask, ack and status bits, see the + * manual's description of the 'int_status' parameter. + */ + ddrc_writel(0, base8 + DDR_INTERRUPT_MASK); + + /* + * Default settings to enable full access to the entire DDR. + * Users can set different ranges and access rights by calling these + * functions before calling cdns_ddr_ctrl_start(). + */ + cdns_ddr_enable_addr_range(ddr_ctrl_base, 0, + ddr_start_addr, ddr_size); + cdns_ddr_enable_prot(ddr_ctrl_base, 0, CDNS_DDR_RANGE_PROT_BITS_FULL, + 0xffff, 0xffff, 0x0f, 0x0f); +} + +void cdns_ddr_ctrl_start(void *ddr_ctrl_basex) +{ + u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex; + u8 *base8 = (u8 *)ddr_ctrl_basex; + + /* Start */ + ddrc_writeb(1, base8 + DDR_START_REG); + + /* Wait for controller to be ready (interrupt status) */ + while (!(readl(base8 + DDR_INTERRUPT_STATUS) & 0x100)) + ; + + /* clear all interrupts */ + ddrc_writel(~0, base8 + DDR_INTERRUPT_ACK); + + /* Step 19 Wait 500us from MRESETB=1 */ + udelay(500); + + /* Step 20 tCKSRX wait (From supply stable clock for MCK) */ + /* DENALI_CTL_19 TREF_ENABLE=0x1(=1), AREFRESH=0x1(=1) */ + ddrc_writel(0x01000100, ddr_ctrl_base + 19); +} diff --git a/drivers/ram/cadence/ddr_ctrl.h b/drivers/ram/cadence/ddr_ctrl.h new file mode 100644 index 0000000000..638d986261 --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +#ifndef CADENCE_DDR_CTRL_H +#define CADENCE_DDR_CTRL_H + +enum cdns_ddr_range_prot { + CDNS_DDR_RANGE_PROT_BITS_PRIV_SECURE = 0, + CDNS_DDR_RANGE_PROT_BITS_SECURE = 1, + CDNS_DDR_RANGE_PROT_BITS_PRIV = 2, + CDNS_DDR_RANGE_PROT_BITS_FULL = 3, +}; + +/** + * Initialise the Cadence DDR Controller, but doesn't start it. + * + * It sets up the controller so that all 4 AXI slave ports allow access to all + * of the DDR with the same settings. This means that: + * - Full access permisions. + * - All read/write priorities are set to 2. + * - Bandwidth is set to 50%, overflow is allowed, i.e. it's a soft limit. + * If you want different properties for different ports and/or addr ranges, call + * the other functions before calling cdns_ddr_ctrl_start(). + * + * @ddr_ctrl_base Physical address of the DDR Controller. + * @async 0 if DDR clock is synchronous with the controller clock + * otherwise 1. + * @reg0 Pointer to array of 32-bit values to be written to registers + * 0 to 87. The values are generated by Cadence TCL scripts. + * @reg350 Pointer to array of 32-bit values to be written to registers + * 350 to 374. The values are generated by Cadence TCL scripts. + * @ddr_start_addr Physical address of the start of DDR. + * @ddr_size Size of the DDR in bytes. The controller will set the port + * protection range to match this size. + */ +void cdns_ddr_ctrl_init(void *ddr_ctrl_base, int async, + const u32 *reg0, const u32 *reg350, + u32 ddr_start_addr, u32 ddr_size); + +/** + * Start the Cadence DDR Controller. + * + * @ddr_ctrl_base Physical address of the DDR Controller. + */ +void cdns_ddr_ctrl_start(void *ddr_ctrl_base); + +/** + * Set the priority for read and write operations for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @read_pri Priority for reads. Range is 0 to 3, where 0 is highest priority. + * @write_pri Priority for writes. Range is 0 to 3, where 0 is highest priority. + */ +void cdns_ddr_set_port_rw_priority(void *base, int port, + u8 read_pri, u8 write_pri); + +/** + * Specify address range for a protection entry, for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, + u32 addr_start, u32 size); + +/** + * Specify address range for a protection entry, for all AXI slave ports. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_addr_range(void *base, int entry, + u32 addr_start, u32 size); + +/** + * Specify protection entry details, for a specific AXI slave port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_port_prot(void *base, int port, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify protection entry details, for all AXI slave ports. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_prot(void *base, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify bandwidth for each AXI port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @max_percent 0 to 100. + */ +void cdns_ddr_set_port_bandwidth(void *base, int port, + u8 max_percent, u8 overflow_ok); + +/* Standard JEDEC registers */ +#define MODE_REGISTER_MASK (3 << 14) +#define MODE_REGISTER_MR0 (0 << 14) +#define MODE_REGISTER_MR1 (1 << 14) +#define MODE_REGISTER_MR2 (2 << 14) +#define MODE_REGISTER_MR3 (3 << 14) +#define MR1_DRIVE_STRENGTH_MASK ((1 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_34_OHMS ((0 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_40_OHMS ((0 << 5) | (0 << 1)) +#define MR1_ODT_IMPEDANCE_MASK ((1 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_60_OHMS ((0 << 9) | (0 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_120_OHMS ((0 << 9) | (1 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_40_OHMS ((0 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_20_OHMS ((1 << 9) | (0 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_30_OHMS ((1 << 9) | (0 << 6) | (1 << 2)) +#define MR2_DYNAMIC_ODT_MASK (3 << 9) +#define MR2_DYNAMIC_ODT_OFF (0 << 9) +#define MR2_SELF_REFRESH_TEMP_MASK (1 << 7) +#define MR2_SELF_REFRESH_TEMP_EXT (1 << 7) + +/** + * Set certain fields of the JEDEC MR1 register. + */ +void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength); + +/** + * Set certain fields of the JEDEC MR2 register. + */ +void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp); + +/** + * Set ODT map of the DDR Controller. + */ +void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map); + +/** + * Set ODT settings in the DDR Controller. + */ +void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, + u8 WR_TO_ODTH, u8 RD_TO_ODTH); + +void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); +void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); + +#endif