Re: [U-Boot] [PATCH 4/6] MSCC: add device tree for Ocelot and Luton (boards and SoCs)

On 25.09.2018 15:01, Gregory CLEMENT wrote:

Adding device tree for Ocelot SoC (extract from Linux) and the 2 evaluation boards using this SoC: PCB120 and PCB132.

Adding device tree for Luton SoC (not yet in Linux) and the evaluation boards using this SoC: PCB91.

Signed-off-by: Gregory CLEMENT gregory.clement@bootlin.com

arch/mips/dts/luton_pcb091.dts | 36 ++++++++ arch/mips/dts/mscc,luton.dtsi | 87 +++++++++++++++++++ arch/mips/dts/mscc,ocelot.dtsi | 132 +++++++++++++++++++++++++++++ arch/mips/dts/mscc,ocelot_pcb.dtsi | 37 ++++++++ arch/mips/dts/ocelot_pcb120.dts | 12 +++ arch/mips/dts/ocelot_pcb123.dts | 12 +++ 6 files changed, 316 insertions(+) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts

should be added along with the board code. Also please try to add Ocelot and Luton boards in separate patches.

diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts new file mode 100644 index 0000000000..b5e0df8d04 --- /dev/null +++ b/arch/mips/dts/luton_pcb091.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+/dts-v1/; +#include "mscc,luton.dtsi"

+/ {

• model = "Luton PCB091 Reference Board";
• compatible = "mscc,luton-pcb091", "mscc,luton";
• aliases {

• serial0 = &uart0;
  

• spi0 = &spi0;
  

• };
• chosen {

• stdout-path = "serial0:115200n8";
  

• };

+};

+&uart0 {

• status = "okay";

+};

+&spi0 {

• status = "okay";
• spi-flash@0 {

• compatible = "spi-flash";
  

•            spi-max-frequency = <18000000>; /* input clock */
  

•            reg = <0>; /* CS0 */
  

• };

+};

diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi new file mode 100644 index 0000000000..6a4ad2a5be --- /dev/null +++ b/arch/mips/dts/mscc,luton.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+#include <dt-bindings/gpio/gpio.h>

+/ {

• #address-cells = <1>;
• #size-cells = <1>;
• compatible = "mscc,luton";
• cpus {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• cpu@0 {
  

• 	compatible = "mips,mips24KEc";
  

• 	device_type = "cpu";
  

• 	reg = <0>;
  

• };
  

• };
• aliases {

• serial0 = &uart0;
  

• };
• ahb_clk: ahb-clk {

• compatible = "fixed-clock";
  

• #clock-cells = <0>;
  

• clock-frequency = <208333333>;
  

• };
• ahb {

• compatible = "simple-bus";
  

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• ranges = <0 0x60000000 0x10200000>;
  

• uart0: serial@10100000 {
  

• 	pinctrl-0 = <&uart_pins>;
  

• 	pinctrl-names = "default";
  

• 	compatible = "ns16550a";
  

• 	reg = <0x10100000 0x20>;
  

• 	clocks = <&ahb_clk>;
  

• 	reg-io-width = <4>;
  

• 	reg-shift = <2>;
  

• 	status = "disabled";
  

• };
  

• gpio: pinctrl@70068 {
  

• 	compatible = "mscc,luton-pinctrl";
  

• 	reg = <0x70068 0x68>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	gpio-ranges = <&gpio 0 0 32>;
  

• 	uart_pins: uart-pins {
  

• 		pins = "GPIO_30", "GPIO_31";
  

• 		function = "uart";
  

• 	};
  

• };
  

• gpio_spi_bitbang: gpio@10000064 {
  

• 	compatible = "mscc,spi-bitbang-gpio";
  

• 	reg = <0x10000064 0x4>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• spi0: spi-bitbang {
  

• 	compatible = "spi-gpio";
  

• 	status = "okay";
  

• 	gpio-sck = <&gpio_spi_bitbang 6 0>;
  

• 	gpio-miso = <&gpio_spi_bitbang 0 0>;
  

• 	gpio-mosi = <&gpio_spi_bitbang 5 0>;
  

• 	cs-gpios = <&gpio_spi_bitbang 1 0>;
  

• 	num-chipselects = <1>;
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• };
  

• };

+}; diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi new file mode 100644 index 0000000000..81afdffd4b --- /dev/null +++ b/arch/mips/dts/mscc,ocelot.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+/ {

• #address-cells = <1>;
• #size-cells = <1>;
• compatible = "mscc,ocelot";
• cpus {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• cpu@0 {
  

• 	compatible = "mips,mips24KEc";
  

• 	device_type = "cpu";
  

• 	clocks = <&cpu_clk>;
  

• 	reg = <0>;
  

• };
  

• };
• aliases {

• serial0 = &uart0;
  

• };
• cpuintc: interrupt-controller@0 {

• #address-cells = <0>;
  

• #interrupt-cells = <1>;
  

• interrupt-controller;
  

• compatible = "mti,cpu-interrupt-controller";
  

• };
• cpu_clk: cpu-clock {

• compatible = "fixed-clock";
  

• #clock-cells = <0>;
  

• clock-frequency = <500000000>;
  

• };
• ahb_clk: ahb-clk {

• compatible = "fixed-clock";
  

• #clock-cells = <0>;
  

• clock-frequency = <250000000>;
  

• };
• ahb {

• compatible = "simple-bus";
  

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• ranges = <0 0x70000000 0x2000000>;
  

• interrupt-parent = <&intc>;
  

• cpu_ctrl: syscon@0 {
  

• 	compatible = "mscc,ocelot-cpu-syscon", "syscon";
  

• 	reg = <0x0 0x2c>;
  

• };
  

• intc: interrupt-controller@70 {
  

• 	compatible = "mscc,ocelot-icpu-intr";
  

• 	reg = <0x70 0x70>;
  

• 	#interrupt-cells = <1>;
  

• 	interrupt-controller;
  

• 	interrupt-parent = <&cpuintc>;
  

• 	interrupts = <2>;
  

• };
  

• uart0: serial@100000 {
  

• 	pinctrl-0 = <&uart_pins>;
  

• 	pinctrl-names = "default";
  

• 	compatible = "ns16550a";
  

• 	reg = <0x100000 0x20>;
  

• 	interrupts = <6>;
  

• 	clocks = <&ahb_clk>;
  

• 	reg-io-width = <4>;
  

• 	reg-shift = <2>;
  

• 	status = "disabled";
  

• };
  

• uart2: serial@100800 {
  

• 	pinctrl-0 = <&uart2_pins>;
  

• 	pinctrl-names = "default";
  

• 	compatible = "ns16550a";
  

• 	reg = <0x100800 0x20>;
  

• 	interrupts = <7>;
  

• 	clocks = <&ahb_clk>;
  

• 	reg-io-width = <4>;
  

• 	reg-shift = <2>;
  

• 	status = "disabled";
  

• };
  

• spi0: spi-master@101000 {
  

• 	#address-cells = <1>;
  

• 	#size-cells = <0>;
  

• 	compatible = "snps,dw-apb-ssi";
  

• 	reg = <0x101000 0x40>;
  

• 	num-chipselect = <4>;
  

• 	bus-num = <0>;
  

• 	reg-io-width = <4>;
  

• 	reg-shift = <2>;
  

• 	spi-max-frequency = <18000000>; /* input clock */
  

• 	clocks = <&ahb_clk>;
  

• 	status = "disabled";
  

• };
  

• reset@1070008 {
  

• 	compatible = "mscc,ocelot-chip-reset";
  

• 	reg = <0x1070008 0x4>;
  

• };
  

• gpio: pinctrl@1070034 {
  

• 	compatible = "mscc,ocelot-pinctrl";
  

• 	reg = <0x1070034 0x68>;
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• 	gpio-ranges = <&gpio 0 0 22>;
  

• 	uart_pins: uart-pins {
  

• 		pins = "GPIO_6", "GPIO_7";
  

• 		function = "uart";
  

• 	};
  

• 	uart2_pins: uart2-pins {
  

• 		pins = "GPIO_12", "GPIO_13";
  

• 		function = "uart2";
  

• 	};
  

• };
  

• };

+}; diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi b/arch/mips/dts/mscc,ocelot_pcb.dtsi new file mode 100644 index 0000000000..4e532363c3 --- /dev/null +++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+/dts-v1/; +#include "mscc,ocelot.dtsi"

+/ {

• compatible = "mscc,ocelot";
• aliases {

• spi0 = &spi0;
  

• serial0 = &uart0;
  

• };
• chosen {

• stdout-path = "serial0:115200n8";
  

• };

+};

+&uart0 {

• status = "okay";

+};

+&spi0 {

• status = "okay";
• spi-flash@0 {

• compatible = "spi-flash";
  

•            spi-max-frequency = <18000000>; /* input clock */
  

•            reg = <0>; /* CS0 */
  

• };

+};

+&ethernet {

• status = "okay";

+}; diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts new file mode 100644 index 0000000000..47d305a614 --- /dev/null +++ b/arch/mips/dts/ocelot_pcb120.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+/dts-v1/; +#include "mscc,ocelot_pcb.dtsi"

+/ {

• model = "Ocelot PCB120 Reference Board";
• compatible = "mscc,ocelot-pcb120", "mscc,ocelot";

+}; diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts new file mode 100644 index 0000000000..17d8d326ce --- /dev/null +++ b/arch/mips/dts/ocelot_pcb123.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2018 Microsemi Corporation
• */

+/dts-v1/; +#include "mscc,ocelot_pcb.dtsi"

+/ {

• model = "Ocelot PCB123 Reference Board";
• compatible = "mscc,ocelot-pcb123", "mscc,ocelot";

+};