From: Hyun Kwon hyun.kwon@xilinx.com
The correct register size is 0x10000, otherwise it overlaps with other register space.
Signed-off-by: Hyun Kwon hyun.kwon@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4d4d62f4930d..1be4d2c68001 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -470,7 +470,7 @@ gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; - reg = <0x0 0xfd4b0000 0x0 0x30000>; + reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";