13 Aug
2018
13 Aug
'18
6:29 p.m.
On 09/12/2017 10:56 AM, Joakim Tjernlund wrote:
Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform.
Signed-off-by: Joakim Tjernlund joakim.tjernlund@infinera.com
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York