From: Armando Visconti armando.visconti@st.com
Signed-off-by: Armando Visconti armando.visconti@st.com --- arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 33 +++++++++++++++++++++++++++++ include/configs/spear13xx_evb.h | 3 ++ 2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c index ab197b3..4720b60 100644 --- a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c @@ -83,6 +83,39 @@ int arch_cpu_init(void) writel(perip1_clk_enb, &misc_p->perip1_clk_enb); writel(perip2_clk_enb, &misc_p->perip2_clk_enb);
+#ifdef CONFIG_SPEAR1300_ISSUE_101435 + { + u32 tmp_var; + + /* + * WRKD the UHC problem (issue #101435) + * + * Bit2 in MISC sys_sw_res reg is used to + * discriminate whether we are coming from a power-on + * reset or not. + */ + tmp_var = readl(&misc_p->sys_sw_res); + if ((tmp_var & 0x4) == 0) { + /* Enable UHC1 and UHC2 clocks) */ + tmp_var = readl(&misc_p->perip1_clk_enb); + writel(tmp_var | 0x600, &misc_p->perip1_clk_enb); + + /* Wait few cycles */ + for (tmp_var = 0; tmp_var < 0x10000; tmp_var++) + ; + + /* Reset the system */ + writel(0x1, &misc_p->sys_sw_res); + while (1) + ; + } else { + /* Clear the RESET condition. */ + writel(0x2, &misc_p->sys_sw_res); + } + + } +#endif + return 0; } #endif diff --git a/include/configs/spear13xx_evb.h b/include/configs/spear13xx_evb.h index eeb46c0..21cc131 100644 --- a/include/configs/spear13xx_evb.h +++ b/include/configs/spear13xx_evb.h @@ -39,6 +39,9 @@ #define CONFIG_ENV_IS_IN_FLASH 1 #endif
+/* Solve issue #101435 - UHC blocks the BUSMATRIX */ +#define CONFIG_SPEAR1300_ISSUE_101435 1 + /* Ethernet configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH