From: Kun-Hua Huang kunhua@andestech.com
Remove ag101 and ag102 support
Signed-off-by: Kun-Hua Huang kunhua@andestech.com --- arch/nds32/Kconfig | 8 - arch/nds32/cpu/n1213/ag102/Makefile | 21 -- arch/nds32/cpu/n1213/ag102/cpu.c | 67 ----- arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 307 ----------------------- arch/nds32/cpu/n1213/ag102/timer.c | 191 -------------- arch/nds32/cpu/n1213/ag102/watchdog.S | 33 --- arch/nds32/include/asm/mach-types.h | 28 --- board/AndesTech/adp-ag101/Kconfig | 18 -- board/AndesTech/adp-ag101/MAINTAINERS | 6 - board/AndesTech/adp-ag101/Makefile | 9 - board/AndesTech/adp-ag101/README | 74 ------ board/AndesTech/adp-ag101/adp-ag101.c | 82 ------ board/AndesTech/adp-ag102/Kconfig | 18 -- board/AndesTech/adp-ag102/MAINTAINERS | 6 - board/AndesTech/adp-ag102/Makefile | 8 - board/AndesTech/adp-ag102/adp-ag102.c | 91 ------- configs/adp-ag101_defconfig | 4 - configs/adp-ag102_defconfig | 6 - doc/README.ag102 | 36 --- include/configs/adp-ag101.h | 384 ----------------------------- include/configs/adp-ag102.h | 334 ------------------------- 21 files changed, 1731 deletions(-) delete mode 100644 arch/nds32/cpu/n1213/ag102/Makefile delete mode 100644 arch/nds32/cpu/n1213/ag102/cpu.c delete mode 100644 arch/nds32/cpu/n1213/ag102/lowlevel_init.S delete mode 100644 arch/nds32/cpu/n1213/ag102/timer.c delete mode 100644 arch/nds32/cpu/n1213/ag102/watchdog.S delete mode 100644 board/AndesTech/adp-ag101/Kconfig delete mode 100644 board/AndesTech/adp-ag101/MAINTAINERS delete mode 100644 board/AndesTech/adp-ag101/Makefile delete mode 100644 board/AndesTech/adp-ag101/README delete mode 100644 board/AndesTech/adp-ag101/adp-ag101.c delete mode 100644 board/AndesTech/adp-ag102/Kconfig delete mode 100644 board/AndesTech/adp-ag102/MAINTAINERS delete mode 100644 board/AndesTech/adp-ag102/Makefile delete mode 100644 board/AndesTech/adp-ag102/adp-ag102.c delete mode 100644 configs/adp-ag101_defconfig delete mode 100644 configs/adp-ag102_defconfig delete mode 100644 doc/README.ag102 delete mode 100644 include/configs/adp-ag101.h delete mode 100644 include/configs/adp-ag102.h
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 98b0282..4fcd01d 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -8,19 +8,11 @@ choice prompt "Target select" optional
-config TARGET_ADP_AG101 - bool "Support adp-ag101" - config TARGET_ADP_AG101P bool "Support adp-ag101p"
-config TARGET_ADP_AG102 - bool "Support adp-ag102" - endchoice
-source "board/AndesTech/adp-ag101/Kconfig" source "board/AndesTech/adp-ag101p/Kconfig" -source "board/AndesTech/adp-ag102/Kconfig"
endmenu diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile deleted file mode 100644 index c21ce02..0000000 --- a/arch/nds32/cpu/n1213/ag102/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar prafulla@marvell.com -# -# Copyright (C) 2011 Andes Technology Corporation -# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com -# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cpu.o timer.o - -ifndef CONFIG_SKIP_LOWLEVEL_INIT -obj-y += lowlevel_init.o -endif - -ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -obj-y += watchdog.o -endif diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c deleted file mode 100644 index 2ee45d2..0000000 --- a/arch/nds32/cpu/n1213/ag102/cpu.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, gj@denx.de - * - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* CPU specific code */ -#include <common.h> -#include <command.h> -#include <watchdog.h> -#include <asm/cache.h> - -#include <faraday/ftwdt010_wdt.h> - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - -#ifdef CONFIG_MMU - /* turn off I/D-cache */ - icache_disable(); - dcache_disable(); - - /* flush I/D-cache */ - invalidate_icac(); - invalidate_dcac(); -#endif - - return 0; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - disable_interrupts(); - - /* - * reset to the base addr of andesboot. - * currently no ROM loader at addr 0. - * do not use reset_cpu(0); - */ -#ifdef CONFIG_FTWDT010_WATCHDOG - /* - * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead - * automatic hardware reset when booting Linux. - * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here. - */ - ftwdt010_wdt_reset(); -#endif /* CONFIG_FTWDT010_WATCHDOG */ - hang(); - - /*NOTREACHED*/ -} diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S deleted file mode 100644 index 238410d..0000000 --- a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.text - -#include <common.h> -#include <config.h> - -#include <asm/macro.h> -#include <generated/asm-offsets.h> - -/* - * parameters for Synopsys DWC DDR2/DDR1 Memory Controller - */ -#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE) -#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR) -#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR) -#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR) -#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR) -#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR) -#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0) -#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1) -#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2) -#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3) -#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4) -#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5) -#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6) -#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7) -#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8) -#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9) -#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0) -#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0) -#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR) -#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR) - -#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR -#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2 -#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR -#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR -#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR -#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR -#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0 -#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0 -#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR -#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR - -#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */ - -/* - * parameters for the ahbc controller - */ -#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR) -#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6) - -#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 - -/* - * parameters for the ANDES PCU controller - */ -#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4) -#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4 - -/* - * numeric 7 segment display - */ -.macro led, num - write32 CONFIG_DEBUG_LED, \num -.endm - -/* - * Waiting for SDRAM to set up - */ -/* -.macro wait_sdram - li $r0, DDR2C_CSR_A -1: - lwi $r1, [$r0+FTSDMC021_CR2] - bnez $r1, 1b -.endm -*/ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - move $r10, $lp - - /* U200 */ -! led 0x00 -! jal scale_to_500mhz - - led 0x10 - jal mem_init - - led 0x20 - jal remap - -#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) - led 0x2f - jal enable_fpu -#endif - - led 0x30 - ret $r10 - -scale_to_500mhz: - move $r11, $lp - - /* - * scale to 500Mhz - */ - led 0x01 - write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4 - - move $lp, $r11 - ret - -mem_init: - move $r11, $lp - - /* - * config AHB Controller - */ - led 0x12 - write32 AHBC_BSR6_A, AHBC_BSR6_D - - /* - * config Synopsys DWC DDR2/DDR1 Memory Controller - */ -ddr2c_init: -set_dcr: - led 0x14 - write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4 - -auto_sizing: - /* - * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13 - */ -set_iocr: - led 0x19 - write32 DDR2C_IOCR_A, DDR2C_IOCR_D -set_drr: - led 0x16 - write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812 -set_dllcr: - led 0x18 - write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D - write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D -set_rslr0: - write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040 -set_rdgr0: - write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf -set_dtar: - led 0x15 - write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000 -set_mode: - led 0x17 - write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852 -set_ccr: - write32 DDR2C_CCR_A, DDR2C_CCR_D - -#ifdef TRIGGER_INIT: -trigger_init: - write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000 - - /* Wait for ddr init state to be set */ - msync ALL - isb - - /* Wait until the config initialization is finish */ -1: - la $r4, DDR2C_CSR_A - lwi $r5, [$r4] - srli $r5, $r5, 23 - bnez $r5, 1b -#endif - -data_training: -! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004 - - /* Wait for ddr init state to be set */ - msync ALL - isb - - /* wait until the ddr data trainning is complete */ -1: - la $r4, DDR2C_CSR_A - lwi $r5, [$r4] - srli $r6, $r5, 23 - bnez $r6, 1b - - lwi $r1, [$r4] - srli $r6, $r5, 20 - li $r5, 0x00ffffff - swi $r1, [$r4] - bnez $r6, ddr2c_init - - led 0x1a - move $lp, $r11 - ret - -remap: - move $r11, $lp -#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ - bal 2f -relo_base: - move $r0, $lp -#else -relo_base: - mfusr $r0, $pc -#endif /* __NDS32_N1213_43U1H__ */ - - /* - * Remapping - */ -#ifdef CONFIG_MEM_REMAP - /* - * Copy ROM code to SDRAM base for memory remap layout. - * This is not the real relocation, the real relocation is the function - * relocate_code() is start.S which supports the systems is memory - * remapped or not. - */ - /* - * Doing memory remap is essential for preparing some non-OS or RTOS - * applications. - * - * This is also a must on ADP-AG101 board. - * The reason is because the ROM/FLASH circuit on PCB board. - * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which - * ROM/FLASH is used to boot. - * - * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, - * and the FLASH is connected to BANK1. - * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), - * and the FLASH is connected to BANK0. - * It will occur problem when doing flash probing if the flash is at - * BANK0 (0x00000000) while memory remapping was skipped. - * - * Other board like ADP-AG101P may not enable this since there is only - * a FLASH connected to bank0. - */ - led 0x21 - li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */ - li $r5, 0x0 - la $r1, relo_base /* get $pc or $lp */ - sub $r2, $r0, $r1 - sethi $r6, hi20(_end) - ori $r6, $r6, lo12(_end) - add $r6, $r6, $r2 -1: - lwi.p $r7, [$r5], #4 - swi.p $r7, [$r4], #4 - blt $r5, $r6, 1b - - /* set remap bit */ - /* - * MEM remap bit is operational - * - use it to map writeable memory at 0x00000000, in place of flash - * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff - * - after remap: flash/rom 0x80000000, sdram: 0x00000000 - */ - led 0x2c - setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1 - -#endif /* #ifdef CONFIG_MEM_REMAP */ - move $lp, $r11 -2: - ret - - /* - * enable_fpu: - * Some of Andes CPU version support FPU coprocessor, if so, - * and toolchain support FPU instruction set, we should enable it. - */ -#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) -enable_fpu: - mfsr $r0, $CPU_VER /* enable FPU if it exists */ - srli $r0, $r0, 3 - andi $r0, $r0, 1 - beqz $r0, 1f /* skip if no COP */ - mfsr $r0, $FUCOP_EXIST - srli $r0, $r0, 31 - beqz $r0, 1f /* skip if no FPU */ - mfsr $r0, $FUCOP_CTL - ori $r0, $r0, 1 - mtsr $r0, $FUCOP_CTL -1: - ret -#endif - -.globl show_led -show_led: - li $r8, (CONFIG_DEBUG_LED) - swi $r7, [$r8] - ret -#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/nds32/cpu/n1213/ag102/timer.c b/arch/nds32/cpu/n1213/ag102/timer.c deleted file mode 100644 index 758b354..0000000 --- a/arch/nds32/cpu/n1213/ag102/timer.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang ratbert@faraday-tech.com - * - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <faraday/fttmr010.h> - -static ulong timestamp; -static ulong lastdec; - -int timer_init(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - unsigned int cr; - - debug("%s()\n", __func__); - - /* disable timers */ - writel(0, &tmr->cr); - -#ifdef CONFIG_FTTMR010_EXT_CLK - /* use 32768Hz oscillator for RTC, WDT, TIMER */ - ftpmu010_32768osc_enable(); -#endif - - /* setup timer */ - writel(TIMER_LOAD_VAL, &tmr->timer3_load); - writel(TIMER_LOAD_VAL, &tmr->timer3_counter); - writel(0, &tmr->timer3_match1); - writel(0, &tmr->timer3_match2); - - /* we don't want timer to issue interrupts */ - writel(FTTMR010_TM3_MATCH1 | - FTTMR010_TM3_MATCH2 | - FTTMR010_TM3_OVERFLOW, - &tmr->interrupt_mask); - - cr = readl(&tmr->cr); -#ifdef CONFIG_FTTMR010_EXT_CLK - cr |= FTTMR010_TM3_CLOCK; /* use external clock */ -#endif - cr |= FTTMR010_TM3_ENABLE; - writel(cr, &tmr->cr); - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - return 0; -} - -/* - * timer without interrupts - */ - -/* - * reset time - */ -void reset_timer_masked(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - - /* capure current decrementer value time */ -#ifdef CONFIG_FTTMR010_EXT_CLK - lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); -#else - lastdec = readl(&tmr->timer3_counter) / - (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ); -#endif - timestamp = 0; /* start "advancing" time stamp from 0 */ - - debug("%s(): lastdec = %lx\n", __func__, lastdec); -} - -void reset_timer(void) -{ - debug("%s()\n", __func__); - reset_timer_masked(); -} - -/* - * return timer ticks - */ -ulong get_timer_masked(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - - /* current tick value */ -#ifdef CONFIG_FTTMR010_EXT_CLK - ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); -#else - ulong now = readl(&tmr->timer3_counter) / - (CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ); -#endif - - debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp fordward with absoulte diff ticks - */ - timestamp += lastdec - now; - } else { - /* - * we have overflow of the count down timer - * - * nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and - * cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - - lastdec = now; - - debug("%s() returns %lx\n", __func__, timestamp); - - return timestamp; -} - -/* - * return difference between timer ticks and base - */ -ulong get_timer(ulong base) -{ - debug("%s(%lx)\n", __func__, base); - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - debug("%s(%lx)\n", __func__, t); - timestamp = t; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - -#ifdef CONFIG_FTTMR010_EXT_CLK - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; -#else - long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000; -#endif - unsigned long now, last = readl(&tmr->timer3_counter); - - debug("%s(%lu)\n", __func__, usec); - while (tmo > 0) { - now = readl(&tmr->timer3_counter); - if (now > last) /* count down timer overflow */ - tmo -= TIMER_LOAD_VAL + last - now; - else - tmo -= last - now; - last = now; - } -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - debug("%s()\n", __func__); - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - debug("%s()\n", __func__); -#ifdef CONFIG_FTTMR010_EXT_CLK - return CONFIG_SYS_HZ; -#else - return CONFIG_SYS_CLK_FREQ; -#endif -} diff --git a/arch/nds32/cpu/n1213/ag102/watchdog.S b/arch/nds32/cpu/n1213/ag102/watchdog.S deleted file mode 100644 index 8f450af..0000000 --- a/arch/nds32/cpu/n1213/ag102/watchdog.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch-ag102/ag102.h> -#include <linux/linkage.h> - -.text - -#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -ENTRY(turnoff_watchdog) - -#define WD_CR 0xC -#define WD_ENABLE 0x1 - - ! Turn off the watchdog, according to Faraday FTWDT010 spec - li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR - lwi $p1, [$p0] ! Get the config of WD - andi $p1, $p1, 0x1f ! Wipe out useless bits - li $r0, ~WD_ENABLE - and $p1, $p1, $r0 ! Set WD disable - sw $p1, [$p0] ! Write back to WD CR - - ! Disable Interrupts by clear GIE in $PSW reg - setgie.d - - ret - -ENDPROC(turnoff_watchdog) -#endif diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 259e4e7..1959d7e 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -12,20 +12,6 @@ extern unsigned int __machine_arch_type; #endif
/* see arch/arm/kernel/arch.c for a description of these */ -#define MACH_TYPE_ADPAG101 0 - -#ifdef CONFIG_ARCH_ADPAG101 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADPAG101 -# endif -# define machine_is_adpag101() (machine_arch_type == MACH_TYPE_ADPAG101) -#else -# define machine_is_adpag101() (0) -#endif - #define MACH_TYPE_ADPAG101P 1
#ifdef CONFIG_ARCH_ADPAG101P @@ -40,18 +26,4 @@ extern unsigned int __machine_arch_type; # define machine_is_adpag101p() (1) #endif
-#define MACH_TYPE_ADPAG102 2 - -#ifdef CONFIG_ARCH_ADPAG102 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_ADPAG102 -# endif -# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102) -#else -# define machine_is_adpag102() (2) -#endif - #endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/board/AndesTech/adp-ag101/Kconfig b/board/AndesTech/adp-ag101/Kconfig deleted file mode 100644 index 8f0197a..0000000 --- a/board/AndesTech/adp-ag101/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_ADP_AG101 - -config SYS_CPU - default "n1213" - -config SYS_BOARD - default "adp-ag101" - -config SYS_VENDOR - default "AndesTech" - -config SYS_SOC - default "ag101" - -config SYS_CONFIG_NAME - default "adp-ag101" - -endif diff --git a/board/AndesTech/adp-ag101/MAINTAINERS b/board/AndesTech/adp-ag101/MAINTAINERS deleted file mode 100644 index 1f0169b..0000000 --- a/board/AndesTech/adp-ag101/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ADP-AG101 BOARD -M: Andes uboot@andestech.com -S: Maintained -F: board/AndesTech/adp-ag101/ -F: include/configs/adp-ag101.h -F: configs/adp-ag101_defconfig diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile deleted file mode 100644 index 4cc590f..0000000 --- a/board/AndesTech/adp-ag101/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2011 Andes Technology Corporation -# Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com -# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := adp-ag101.o diff --git a/board/AndesTech/adp-ag101/README b/board/AndesTech/adp-ag101/README deleted file mode 100644 index 46fc637..0000000 --- a/board/AndesTech/adp-ag101/README +++ /dev/null @@ -1,74 +0,0 @@ -Andes Technology SoC AG101 -========================== - -AG101 is the first SoC produced by Andes Technology using N1213 CPU core. -AG101 has integrated both AHB and APB bus and many periphals for application -and product development. - -ADP-AG101 -========= - -ADP-AG101 is the SoC with AG101 hardcore CPU. - -Please check http://www.andestech.com/p2-4.htm for detail of this SoC. - -Configurations -============== - -CONFIG_MEM_REMAP: - Doing memory remap is essential for preparing some non-OS or RTOS - applications. - - This is also a must on ADP-AG101 board. - (While other boards may not have this problem). - - The reason is because the ROM/FLASH circuit on PCB board. - AG101-A0 board has 2 jumpers MA17 and SW5 to configure which - ROM/FLASH is used to boot. - - When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0, - and the FLASH is connected to BANK1. - When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0), - and the FLASH is connected to BANK0. - It will occur problem when doing flash probing if the flash is at - BANK0 (0x00000000) while memory remapping was skipped. - - Other board like ADP-AG101P may not enable this since there is only - a FLASH connected to bank0. - -CONFIG_SKIP_LOWLEVEL_INIT: - If you want to boot this system from FLASH and bypass e-bios (the - other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT - in "include/configs/adp-ag101.h". - -Build and boot steps -==================== - -build: -1. Prepare the toolchains and make sure the $PATH to toolchains is correct. -2. Use `make adp-ag101` in u-boot root to build the image. - -burn u-boot to flash: -1. Make sure the MA17 (J16) is Lo. -2. Make sure the dip switch SW5 is set to "0101". -3. Power On. Press button "S1", then press button "SW1", then you will found the - debug LED show 67 means the system successfully booted into e-bios. - Now you can control the e-bios boot loader from your console. -4. Under "Command>>" prompt, enter "97" (CopyImageFromCard) -5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c". -6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you - just build. It is usually "u-boot.bin". -7. Under "Enter Dest. Address =>" prompt, enter the memory address where you - want to put the binary from SD card to RAM. - Address "0x500000" is our suggestion. -8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command - environment. -9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the - binary from RAM to FLASH. -10. Under "CLI>" prompt, enter "exit" to finish the burn process. - -boot u-boot from flash: -1. Make sure the MA17 (J16) is Hi). -2. Make sure the dip switch SW5 is set to "1010". -3. Power On. Press button "S1", then you will see the debug LED count to 20. -4. Now you can use u-boot on ADP-AG101 board. diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c deleted file mode 100644 index 9884a5b..0000000 --- a/board/AndesTech/adp-ag101/adp-ag101.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> - -#include <faraday/ftsdc010.h> -#include <faraday/ftsmc020.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initializations - */ - -int board_init(void) -{ - /* - * refer to BOOT_PARAMETER_PA_BASE within - * "linux/arch/nds32/include/asm/misc_spec.h" - */ - gd->bd->bi_arch_number = MACH_TYPE_ADPAG101; - gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; - - ftsmc020_init(); /* initialize Flash */ - return 0; -} - -int dram_init(void) -{ - unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; - unsigned long actual_size; - - actual_size = get_ram_size((void *)sdram_base, expected_size); - - gd->ram_size = actual_size; - - if (expected_size != actual_size) { - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - } - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_0; - gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; -} - -int board_eth_init(bd_t *bd) -{ - return ftmac100_initialize(bd); -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->interface = FLASH_CFI_X8; - return 1; - } else { - return 0; - } -} - -int board_mmc_init(bd_t *bis) -{ - ftsdc010_mmc_init(0); - return 0; -} diff --git a/board/AndesTech/adp-ag102/Kconfig b/board/AndesTech/adp-ag102/Kconfig deleted file mode 100644 index fc17be3..0000000 --- a/board/AndesTech/adp-ag102/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_ADP_AG102 - -config SYS_CPU - default "n1213" - -config SYS_BOARD - default "adp-ag102" - -config SYS_VENDOR - default "AndesTech" - -config SYS_SOC - default "ag102" - -config SYS_CONFIG_NAME - default "adp-ag102" - -endif diff --git a/board/AndesTech/adp-ag102/MAINTAINERS b/board/AndesTech/adp-ag102/MAINTAINERS deleted file mode 100644 index 94b87c7..0000000 --- a/board/AndesTech/adp-ag102/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ADP-AG102 BOARD -M: Andes uboot@andestech.com -S: Maintained -F: board/AndesTech/adp-ag102/ -F: include/configs/adp-ag102.h -F: configs/adp-ag102_defconfig diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile deleted file mode 100644 index fc4bf88..0000000 --- a/board/AndesTech/adp-ag102/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2011 Andes Technology Corporation -# Macpaul Lin, Andes Technology Corporation macpaul@andestech.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := adp-ag102.o diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c deleted file mode 100644 index 3f879ab..0000000 --- a/board/AndesTech/adp-ag102/adp-ag102.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> - -#include <faraday/ftpci100.h> -#include <faraday/ftsdc010.h> -#ifdef CONFIG_FTSMC020 -#include <faraday/ftsmc020.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initializations - */ - -int board_init(void) -{ - /* - * refer to BOOT_PARAMETER_PA_BASE within - * "linux/arch/nds32/include/asm/misc_spec.h" - */ - gd->bd->bi_arch_number = MACH_TYPE_ADPAG102; - gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; - -#if !defined(CONFIG_SYS_NO_FLASH) - ftsmc020_init(); /* initialize Flash */ -#endif /* CONFIG_SYS_NO_FLASH */ - return 0; -} - -int dram_init(void) -{ - unsigned long sdram_base = PHYS_SDRAM_0; - unsigned long expected_size = PHYS_SDRAM_0_SIZE; - unsigned long actual_size; - - actual_size = get_ram_size((void *)sdram_base, expected_size); - - gd->ram_size = actual_size; - - if (expected_size != actual_size) { - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - } - - return 0; -} - -int board_eth_init(bd_t *bd) -{ - return ftgmac100_initialize(bd); -} - -#if !defined(CONFIG_SYS_NO_FLASH) -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->interface = FLASH_CFI_X8; - return 1; - } else { - return 0; - } -} -#endif /* CONFIG_SYS_NO_FLASH */ - -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -void pci_init_board(void) -{ - /* should be pci_ftpci100_init() */ - pci_ftpci_init(); -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - ftsdc010_mmc_init(0); - return 0; -} -#endif diff --git a/configs/adp-ag101_defconfig b/configs/adp-ag101_defconfig deleted file mode 100644 index ac1dcaa..0000000 --- a/configs/adp-ag101_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_NDS32=y -CONFIG_TARGET_ADP_AG101=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="NDS32 # " diff --git a/configs/adp-ag102_defconfig b/configs/adp-ag102_defconfig deleted file mode 100644 index 1bef350..0000000 --- a/configs/adp-ag102_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_NDS32=y -CONFIG_TARGET_ADP_AG102=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="NDS32 # " diff --git a/doc/README.ag102 b/doc/README.ag102 deleted file mode 100644 index 7d142a7..0000000 --- a/doc/README.ag102 +++ /dev/null @@ -1,36 +0,0 @@ -Andes Technology SoC AG102 -========================== - -AG102 is the second SoC produced by Andes Technology using N1213 CPU core -with FPU and DDR contoller support. -AG102 has integrated both AHB and APB bus and many periphals for application -and product development. - -ADP-AG102 -========= - -ADP-AG102 is the SoC with AG102 hardcore CPU. - -Configurations -============== - -CONFIG_MEM_REMAP: - Doing memory remap is essential for preparing some non-OS or RTOS - applications. - -CONFIG_SKIP_LOWLEVEL_INIT: - If you want to boot this system from SPI ROM and bypass e-bios (the - other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT - in "include/configs/adp-ag102.h". - -Build and boot steps -==================== - -build: -1. Prepare the toolchains and make sure the $PATH to toolchains is correct. -2. Use `make adp-ag102` in u-boot root to build the image. - -Burn u-boot to SPI ROM: -==================== - -This section will be added later. diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h deleted file mode 100644 index 0f256d8..0000000 --- a/include/configs/adp-ag101.h +++ /dev/null @@ -1,384 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation nobuhiro@andestech.com - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch-ag101/ag101.h> - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_ADP_AG101 - -#define CONFIG_USE_INTERRUPT - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MEM_REMAP -#endif - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x03200000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif - -/* - * Timer - */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ - -/* - * Use Externel CLOCK or PCLK - */ -#undef CONFIG_FTRTC010_EXTCLK - -#ifndef CONFIG_FTRTC010_EXTCLK -#define CONFIG_FTRTC010_PCLK -#endif - -#ifdef CONFIG_FTRTC010_EXTCLK -#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ -#else -#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Real Time Clock Divider - * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - */ -#define OSC_5MHZ (5*1000000) -#define OSC_CLK (2*OSC_5MHZ) -#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ -#define CONFIG_BAUDRATE 38400 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK ((46080000 * 20) / 25) /* AG101 */ - -/* - * Ethernet - */ -#define CONFIG_FTMAC100 - -#define CONFIG_BOOTDELAY 3 - -/* - * SD (MMC) controller - */ -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FTSDC010 -#define CONFIG_FTSDC010_NUMBER 1 -#define CONFIG_FTSDC010_SDIO -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - */ -/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* - * AHB Controller configuration - */ -#define CONFIG_FTAHBC020S - -#ifdef CONFIG_FTAHBC020S -#include <faraday/ftahbc020s.h> - -/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 - -/* - * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, - * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote - * in C language. - */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ - (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ - FTAHBC020S_SLAVE_BSR_SIZE(0xb)) -#endif - -/* - * Watchdog - */ -#define CONFIG_FTWDT010_WATCHDOG - -/* - * PMU Power controller configuration - */ -#define CONFIG_PMU -#define CONFIG_FTPMU010_POWER - -#ifdef CONFIG_FTPMU010_POWER -#include <faraday/ftpmu010.h> -#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E -#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ - FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ - FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ - FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ - FTPMU010_SDRAMHTC_CKE_DCSR | \ - FTPMU010_SDRAMHTC_DQM_DCSR | \ - FTPMU010_SDRAMHTC_SDCLK_DCSR) -#endif - -/* - * SDRAM controller configuration - */ -#define CONFIG_FTSDMC021 - -#ifdef CONFIG_FTSDMC021 -#include <faraday/ftsdmc021.h> - -#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRP(1) | \ - FTSDMC021_TP1_TRCD(1) | \ - FTSDMC021_TP1_TRF(3) | \ - FTSDMC021_TP1_TWR(1) | \ - FTSDMC021_TP1_TCL(2)) - -#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ - FTSDMC021_TP2_INI_REFT(8) | \ - FTSDMC021_TP2_REF_INTV(0x180)) - -/* - * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, - * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in - * C language. - */ -#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ - FTSDMC021_CR1_DSZ(3) | \ - FTSDMC021_CR1_MBW(2) | \ - FTSDMC021_CR1_BNKSIZE(6)) - -#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ - FTSDMC021_CR2_IREF | \ - FTSDMC021_CR2_ISMR) - -#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE -#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ - CONFIG_SYS_FTSDMC021_BANK0_BASE) - -#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ - (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) -#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ - CONFIG_SYS_FTSDMC021_BANK1_BASE) - -#endif - -/* - * Physical Memory Map - */ -#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ -#if defined(CONFIG_MEM_REMAP) -#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ -#endif -#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ -#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ -#endif -#define PHYS_SDRAM_1 \ - (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ - -#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ -#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -#ifdef CONFIG_MEM_REMAP -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ - GENERATED_GBL_DATA_SIZE) -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_MEM_REMAP */ - -/* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) - -/* - * Static memory controller configuration - */ -#define CONFIG_FTSMC020 - -#ifdef CONFIG_FTSMC020 -#include <faraday/ftsmc020.h> - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} -#else -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} -#endif - -/* - * There are 2 bank connected to FTSMC020 on ADP-AG101. - * You can use jumper and switch to force it booted from ROM or FLASH. - * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH. - * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled. - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ -#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(1) | \ - FTSMC020_TPR_CTW(1) | \ - FTSMC020_TPR_ATI(1) | \ - FTSMC020_TPR_AT2(1) | \ - FTSMC020_TPR_WTC(1) | \ - FTSMC020_TPR_AHT(1) | \ - FTSMC020_TPR_TRNA(1)) -#endif - -/* - * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0. - * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM, - * Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition. - * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH. - */ -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(1) | \ - FTSMC020_TPR_CTW(1) | \ - FTSMC020_TPR_ATI(1) | \ - FTSMC020_TPR_AT2(1) | \ - FTSMC020_TPR_WTC(1) | \ - FTSMC020_TPR_AHT(1) | \ - FTSMC020_TPR_TRNA(1)) -#endif /* CONFIG_FTSMC020 */ - -/* - * FLASH and environment organization - */ -/* use CFI framework */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* support JEDEC */ - -/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define PHYS_FLASH_1 0x80400000 /* BANK 1 */ -#else /* !CONFIG_SKIP_LOWLEVEL_INIT */ -#ifdef CONFIG_MEM_REMAP -#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ -#else -#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ -#endif /* CONFIG_MEM_REMAP */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ - -/* max number of memory banks */ -/* - * There are 4 banks supported for this Controller, - * but we have only 1 bank connected to flash on board - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) -#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* environments */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SIZE 8192 -#define CONFIG_ENV_OVERWRITE - -#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h deleted file mode 100644 index 6f05d87..0000000 --- a/include/configs/adp-ag102.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation macpaul@andestech.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch-ag102/ag102.h> - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_ADP_AG102 - -#define CONFIG_USE_INTERRUPT - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MEM_REMAP -#endif - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x04200000 -#else -#define CONFIG_SYS_TEXT_BASE 0x00000000 -#endif - -/* - * Timer - */ -#define CONFIG_SYS_CLK_FREQ (66000000 * 2) -#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ - -/* - * Use Externel CLOCK or PCLK - */ -#undef CONFIG_FTRTC010_EXTCLK - -#ifndef CONFIG_FTRTC010_EXTCLK -#define CONFIG_FTRTC010_PCLK -#endif - -#ifdef CONFIG_FTRTC010_EXTCLK -#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ -#else -#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Real Time Clock Divider - * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - */ -#define OSC_5MHZ (5*1000000) -#define OSC_CLK (2*OSC_5MHZ) -#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART */ -#define CONFIG_BAUDRATE 38400 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */ - -/* - * Ethernet - */ -#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */ -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_FTGMAC100 -#define CONFIG_FTGMAC100_EGIGA - -#define CONFIG_BOOTDELAY 3 - -/* - * SD (MMC) controller - */ -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION -#define CONFIG_FTSDC010 -#define CONFIG_FTSDC010_NUMBER 1 -#define CONFIG_FTSDC010_SDIO -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF - - -/* - * PCI - */ -#define CONFIG_PCI -#define CONFIG_FTPCI100 -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FTPCI100_MEM_BASE 0xa0000000 -#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */ -#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */ -#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50 - -#define CONFIG_PCI_MEM_BUS 0xa0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */ - -#define CONFIG_PCI_IO_BUS 0x90000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */ - -/* - * USB - */ -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -#if defined(CONFIG_FTPCI100) -#define __io /* enable outl & inl */ -#define CONFIG_CMD_USB -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI -#define CONFIG_PCI_EHCI_DEVICE 0 -#define CONFIG_USB_EHCI_PCI -#define CONFIG_PREBOOT "usb start;" -#endif /* #if defiend(CONFIG_FTPCI100) */ -#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */ - -/* - * IDE/ATA stuff - */ -#define __io -#define CONFIG_IDE_AHB -#define CONFIG_IDE_FTIDE020 - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CONFIG_IDE_PREINIT 1 /* preinit for ide */ - -/* max: 2 IDE busses */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */ -/* max: 2 drives per IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */ - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */ - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_SUPPORT_VFAT - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * AHB Controller configuration - */ -#define CONFIG_FTAHBC020S - -#ifdef CONFIG_FTAHBC020S -#include <faraday/ftahbc020s.h> - -/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 - -/* - * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, - * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote - * in C language. - */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ - (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ - FTAHBC020S_SLAVE_BSR_SIZE(0xb)) -#endif - -/* - * Watchdog - */ -#define CONFIG_FTWDT010_WATCHDOG - -/* - * PCU Power Control Unit configuration - */ -#define CONFIG_ANDES_PCU - -#ifdef CONFIG_ANDES_PCU -#include <andestech/andes_pcu.h> - -#endif - -/* - * DDR DRAM controller configuration - */ -#define CONFIG_DWCDDR21MCTL - -#ifdef CONFIG_DWCDDR21MCTL -#include <synopsys/dwcddr21mctl.h> -/* DCR: - * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend - * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk - * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks) - * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank) - * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks) - */ -#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004 -#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \ - DWCDDR21MCTL_CCR_DFTLM(0x4) | \ - DWCDDR21MCTL_CCR_HOSTEN(0x1)) - -/* 0x04: 0x000020d4 */ -#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca - -/* 0x08: 0x0000000f */ -#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f - -/* 0x10: 0x00034812 */ -#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \ - DWCDDR21MCTL_DRR_TRFPRD(0x0348)) -/* 0x24 */ -#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0) - -/* 0x4c: 0x00000040 */ -#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040 - -/* 0x5c: 0x000055CF */ -#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf - -/* 0xa4: 0x00100000 */ -#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \ - DWCDDR21MCTL_DTAR_DTROW(0x0100) | \ - DWCDDR21MCTL_DTAR_DTCOL(0x0)) -/* 0x1f0: 0x00000852 */ -#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \ - DWCDDR21MCTL_MR_CL(0x5) | \ - DWCDDR21MCTL_MR_BL(0x2)) -#endif - -/* - * Physical Memory Map - */ -#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ -#if defined(CONFIG_MEM_REMAP) -#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/ -#endif -#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ -#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ -#endif - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -#ifdef CONFIG_MEM_REMAP -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ - GENERATED_GBL_DATA_SIZE) -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_MEM_REMAP */ - -/* - * Load address and memory test area should agree with - * board/faraday/a320/config.mk - * Be careful not to overwrite U-boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x0CF00000 - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) - -/* - * Static memory controller configuration - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_NO_FLASH - -/* - * Env Storage Settings - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 4096 - -#endif /* __CONFIG_H */