On Thu, 2019-08-22 at 09:54 +0200, Marek Vasut wrote:
On 8/22/19 9:40 AM, Chee, Tien Fong wrote:
On Mon, 2019-07-29 at 15:48 +0800, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Different SPI flash has different block erase size configuration, it can be configured as block erase size or sub-block erase size, so SYS_SPI_BLOCK_SIZE is created to provide UBI a consistent block reading. UBI block reading would be eventually translated to offset access into SPI regardless how the block erase size is configured on SPI. This would made the UBI transparent from SPI layer.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
drivers/mtd/spi/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index d3b007a731..ea3779c521 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -196,4 +196,11 @@ config SPI_FLASH_MTD If unsure, say N +config SYS_SPI_BLOCK_SIZE
- hex "SPI chip eraseblock size for UBI reading"
- depends on SPL_SPI_FLASH_SUPPORT
- default 65536
- help
- Number of data bytes in a physical eraseblock for UBI
reading.
endmenu # menu "SPI Flash Support"
Any comment?
UBI is able to obtain underlying media erase block size from the MTD subsystem, just let it do that. Besides, any such compile-time config would fail the next time you change the SPI NOR (e.g. because it's EOL), as that would force you to rebuild U-Boot, which might ultimately not be possible.
Okay, let me check how to get this info from MTD. If you have some ideas, you can let me know too :) .