This patch adds support for NAND on MPC8610HPCD target. We're using BAT7 and LAW4 entries for 4MB NAND mapping.
MPC8610HPCD has four NAND chips in one package, bases as follows: - 0xe8400000 - 0xe8440000 - 0xe8480000 - 0xe84c0000
Also, this patch adds some localbus definitions to mpc86xx.h (straight copy from mpc83xx.h).
Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8610hpcd/law.c | 2 +- include/configs/MPC8610HPCD.h | 37 +++++++-- include/mpc86xx.h | 164 +++++++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index b4d222d..072a997 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -33,7 +33,7 @@ struct law_entry law_table[] = { #endif SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), /* + NAND */ SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 15ff0ea..3299942 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -158,10 +158,34 @@
#define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ -#if 0 /* TODO */ -#define CFG_BR2_PRELIM 0xf0000000 -#define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ -#endif + +/* + * NAND Flash on Local Bus + */ +#define CFG_NAND_BASE 0xe8400000 +#define CFG_NAND_BR_PRELIM(idx) ((CFG_NAND_BASE + 0x40000 * (idx)) | \ + (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ + BR_PS_8 | /* Port Size 8 bit */ \ + BR_MS_FCM | /* MSEL FCM */ \ + BR_V) /* valid */ + +#define CFG_NAND_OR_PRELIM (0xFFFF8000 | /* length 32K */ \ + OR_FCM_CSCT | \ + OR_FCM_CST | \ + OR_FCM_CHT | \ + OR_FCM_SCY_1 | \ + OR_FCM_TRLX | \ + OR_FCM_EHTR) + +#define CFG_BR2_PRELIM CFG_NAND_BR_PRELIM(0) +#define CFG_OR2_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR4_PRELIM CFG_NAND_BR_PRELIM(1) +#define CFG_OR4_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR5_PRELIM CFG_NAND_BR_PRELIM(2) +#define CFG_OR5_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR6_PRELIM CFG_NAND_BR_PRELIM(3) +#define CFG_OR6_PRELIM CFG_NAND_OR_PRELIM + #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
@@ -428,12 +452,13 @@ #define CFG_IBAT6U CFG_DBAT6U
/* - * BAT7 4M Cache-inhibited, guarded + * BAT7 8M Cache-inhibited, guarded * 0xe800_0000 4M PIXIS + * 0xe840_0000 4M NAND */ #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_8M | BATU_VS | BATU_VP) #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT7U CFG_DBAT7U
diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fd349a..54bc649 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -77,6 +77,170 @@ #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000
+/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_DECC_OFF 0x00000000 +#define BR_DECC_CHK 0x00000200 +#define BR_DECC_CHK_GEN 0x00000400 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_FCM 0x00000020 /* FCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 + +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) + +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +#define OR_FCM_AM 0xFFFF8000 +#define OR_FCM_AM_SHIFT 15 +#define OR_FCM_BCTLD 0x00001000 +#define OR_FCM_BCTLD_SHIFT 12 +#define OR_FCM_PGS 0x00000400 +#define OR_FCM_PGS_SHIFT 10 +#define OR_FCM_CSCT 0x00000200 +#define OR_FCM_CSCT_SHIFT 9 +#define OR_FCM_CST 0x00000100 +#define OR_FCM_CST_SHIFT 8 +#define OR_FCM_CHT 0x00000080 +#define OR_FCM_CHT_SHIFT 7 +#define OR_FCM_SCY 0x00000070 +#define OR_FCM_SCY_SHIFT 4 +#define OR_FCM_SCY_1 0x00000010 +#define OR_FCM_SCY_2 0x00000020 +#define OR_FCM_SCY_3 0x00000030 +#define OR_FCM_SCY_4 0x00000040 +#define OR_FCM_SCY_5 0x00000050 +#define OR_FCM_SCY_6 0x00000060 +#define OR_FCM_SCY_7 0x00000070 +#define OR_FCM_RST 0x00000008 +#define OR_FCM_RST_SHIFT 3 +#define OR_FCM_TRLX 0x00000004 +#define OR_FCM_TRLX_SHIFT 2 +#define OR_FCM_EHTR 0x00000002 +#define OR_FCM_EHTR_SHIFT 1 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + #ifndef __ASSEMBLY__
typedef struct {