Some malloc memory is needed at startup for DM model. Lets reorganise the use of the CPM dpram.
The MPC866/885 dpram, we have 8kbytes dual port RAM, which is usable as: IMMR + 0x2000..0x2800: BD/Data/Microcode IMMR + 0x2800..0x2e00: BD/Data IMMR + 0x2e00..0x3800: BD/Data/Microcode IMMR + 0x3800..0x3a00: BD/Data IMMR + 0x3a00..0x3c00: BD/Data/Microcode IMMR + 0x3c00..0x4000: Parameters for the Peripheral Controllers
Lets reallocate all BDs in the 3800..3a00 area and give the full 2800..2e00 for dynamic RAM allocation including global data
That way, the microcode areas remain available if needed on day
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- arch/powerpc/include/asm/cpm_8xx.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/cpm_8xx.h b/arch/powerpc/include/asm/cpm_8xx.h index bd8adec6b07..85903d21088 100644 --- a/arch/powerpc/include/asm/cpm_8xx.h +++ b/arch/powerpc/include/asm/cpm_8xx.h @@ -51,14 +51,14 @@ /* * DPRAM defines and allocation functions */ -#define CPM_SERIAL_BASE 0x0800 -#define CPM_I2C_BASE 0x0820 -#define CPM_SPI_BASE 0x0840 -#define CPM_FEC_BASE 0x0860 -#define CPM_SERIAL2_BASE 0x08E0 -#define CPM_SCC_BASE 0x0900 -#define CPM_POST_BASE 0x0980 -#define CPM_WLKBD_BASE 0x0a00 +#define CPM_SERIAL_BASE 0x1800 +#define CPM_I2C_BASE 0x1820 +#define CPM_SPI_BASE 0x1840 +#define CPM_FEC_BASE 0x1860 +#define CPM_SERIAL2_BASE 0x18e0 +#define CPM_SCC_BASE 0x1900 +#define CPM_POST_BASE 0x1980 +#define CPM_WLKBD_BASE 0x1a00
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */