From: Chris Zankel chris@zankel.net
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor.
- Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705
These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.).
Signed-off-by: Chris Zankel chris@zankel.net Signed-off-by: Max Filippov jcmvbkbc@gmail.com --- arch/xtensa/Kconfig | 3 + board/cadence/xtfpga/Kconfig | 51 +++++++ board/cadence/xtfpga/MAINTAINERS | 6 + board/cadence/xtfpga/Makefile | 8 + board/cadence/xtfpga/README | 121 ++++++++++++++++ board/cadence/xtfpga/lcd.c | 88 +++++++++++ board/cadence/xtfpga/lcd.h | 12 ++ board/cadence/xtfpga/xtfpga.c | 173 ++++++++++++++++++++++ configs/xtfpga_defconfig | 3 + include/configs/xtfpga.h | 305 +++++++++++++++++++++++++++++++++++++++ 10 files changed, 770 insertions(+) create mode 100644 board/cadence/xtfpga/Kconfig create mode 100644 board/cadence/xtfpga/MAINTAINERS create mode 100644 board/cadence/xtfpga/Makefile create mode 100644 board/cadence/xtfpga/README create mode 100644 board/cadence/xtfpga/lcd.c create mode 100644 board/cadence/xtfpga/lcd.h create mode 100644 board/cadence/xtfpga/xtfpga.c create mode 100644 configs/xtfpga_defconfig create mode 100644 include/configs/xtfpga.h
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index e4e3625..d41949f 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -11,9 +11,12 @@ config SYS_CPU choice prompt "Target select"
+config TARGET_XTFPGA + bool "Support XTFPGA"
endchoice
+source "board/cadence/xtfpga/Kconfig"
config HAVE_SYS_ASCDISP bool diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig new file mode 100644 index 0000000..1244ad7 --- /dev/null +++ b/board/cadence/xtfpga/Kconfig @@ -0,0 +1,51 @@ +if TARGET_XTFPGA + +choice + prompt "XTFPGA board type select" + +config XTFPGA_LX60 + bool "Support Avnet LX60" + select HAVE_SYS_ASCDISP +config XTFPGA_LX110 + bool "Support Avnet LX110" + select HAVE_SYS_ASCDISP +config XTFPGA_LX200 + bool "Support Avnet LX200" +config XTFPGA_ML605 + bool "Support Xilinx ML605" + select HAVE_SYS_ASCDISP +config XTFPGA_KC705 + bool "Support Xilinx KC705" + select HAVE_SYS_ASCDISP + +endchoice + +config SYS_BOARD + string + default "xtfpga" + +config SYS_VENDOR + string + default "cadence" + +config SYS_CONFIG_NAME + string + default "xtfpga" + +config SYS_SDRAM_SIZE + hex + default 0x04000000 if XTFPGA_LX60 + default 0x03000000 if XTFPGA_LX110 + default 0x06000000 if XTFPGA_LX200 + default 0x20000000 if XTFPGA_ML605 + default 0x38000000 if XTFPGA_KC705 + +config SYS_MEMORY_SIZE + hex + default 0x04000000 if XTFPGA_LX60 + default 0x03000000 if XTFPGA_LX110 + default 0x06000000 if XTFPGA_LX200 + default 0x08000000 if XTFPGA_ML605 + default 0x08000000 if XTFPGA_KC705 + +endif diff --git a/board/cadence/xtfpga/MAINTAINERS b/board/cadence/xtfpga/MAINTAINERS new file mode 100644 index 0000000..31f5257 --- /dev/null +++ b/board/cadence/xtfpga/MAINTAINERS @@ -0,0 +1,6 @@ +XTFPGA BOARD +M: Max Filippov jcmvbkbc@gmail.com +S: Maintained +F: board/cadence/xtfpga/ +F: include/configs/xtfpga.h +F: configs/xtfpga_defconfig diff --git a/board/cadence/xtfpga/Makefile b/board/cadence/xtfpga/Makefile new file mode 100644 index 0000000..c521a80 --- /dev/null +++ b/board/cadence/xtfpga/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2007 - 2013, Tensilica Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ${BOARD}.o +obj-$(CONFIG_SYS_ASCDISP) += lcd.o diff --git a/board/cadence/xtfpga/README b/board/cadence/xtfpga/README new file mode 100644 index 0000000..47305a2 --- /dev/null +++ b/board/cadence/xtfpga/README @@ -0,0 +1,121 @@ + Tensilica 'xtfpga' Evaluation Boards + ==================================== + +Tensilica's 'xtfpga' evaluation boards are actually a set of different +boards that share configurations. The following is a list of supported +hardware by this board type: + +- XT-AV60 / LX60 +- XT-AV110 / LX110 +- XT-AV200 / LX200 +- ML605 +- KC705 + +All boards provide the following common configurations: + +- An Xtensa or Diamond processor core. +- An on-chip-debug (OCD) JTAG interface. +- A 16550 compatible UART and serial port. +- An OpenCores Wishbone 10/100-base-T ethernet interface. +- A 32 char two line LCD display. (except for the LX200) + +LX60/LX110/LX200: + +- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110) +- 128MB / 64MB (LX60) memory +- 16MB / 4MB (LX60) Linear Flash + +ML605 + +- Virtex-6 (XC6VLX240T) +- 512MB DDR3 memory +- 32MB Linear BPI Flash + +KC705 (Xilinx) + +- Kintex-7 XC7K325T FPGA +- 1GB DDR3 memory +- 128MB Linear BPI Flash + + +Setting up the Board +-------------------- + +The serial port defaults to 115200 baud, no parity and 1 stop bit. +A terminal emulator must be set accordingly to see the U-Boot prompt. + + +Board Configurations LX60/LX110/LX200 +------------------------------------- + +The LX60/LX110/LX200 contain an 8-way DIP switch that controls the boot +mapping and selects from a range of default ethernet MAC addresses. + +Boot Mapping (DIP switch 8): + + DIP switch 8 maps the system ROM address space (in which the + reset vector resides) to either SRAM (off, 0, down) or Flash + (on, 1, up). This mapping is implemented in the FPGA bitstream + and cannot be disabled by software, therefore DIP switch 8 is no + available for application use. Note DIP switch 7 is reserved by + Tensilica for future possible hardware use. + + Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG + tool such as the Xtensa OCD Daemon connected via a suppored probe. + See the tools documentation for supported probes and how to + connect them. Be aware that the board has only 128 KB of SRAM, + therefore U-Boot must fit within this space to debug an image + intended for the Flash. This issues is discussed in a separate + section toward the end. + + Mapping to flash allows U-Boot to start on reset, provided it + has been programmed into the first two 64 KB sectors of the Flash. + + The Flash is always mapped at a device (memory mapped I/O) address + (the address is board specific and is expressed as CFG_FLASH_BASE). + The device address is used by U-Boot to program the flash, and may + be used to specify an application to run or U-Boot image to boot. + +Default MAC Address (DIP switches 1-6): + + When the board is first powered on, or after the environment has + been reinitialized, the ethernet MAC address receives a default + value whose least significant 6 bits come from DIP switches 1-6. + The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F + according to the DIP switches, where "on"==1 and "off"==0, and + switch 1 is the least-significant bit. + + After initial startup, the MAC address is stored in the U-Boot + environment variable 'ethaddr'. The user may change this to any + other address with the "setenv" comamnd. After the environment + has been saved to Flash by the "saveenv" command, this will be + used and the DIP switches no longer consulted. DIP swithes 1-6 + may then be used for application purposes. + + +Limitation of SDRAM Size for OCD Debugging on the LX60 +------------------------------------------------------ + +The XT-AV60 board has only 128 KB of SDRAM that can be mapped +to the system ROM address space for debugging a ROM image under +OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000) +or the first 2 sectors of the flash. + +This can pose a problem if all the sources are compiled with -O0 +for debugging. The code size is then too large, in which case it +would be necessary to temporarily alter the linker script to place +the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot +directly there and does not unpack. In practice this is not really +necessary as long as only a limited set of sources need to be +debugged, because the image can still fit into the 128 KB SRAM. + +The recommended procedure for debugging is to first build U-Boot +with the default optimization level (-Os), and then touch and +rebuild incrementally with -O0 so that only the touched sources +are recompiled with -O0. To build with -O0, modify the top level +config.mk and add '-O0' to the make variable OPTFLAGS. + +Because this problem is easy to fall into and difficult to debug +if one doesn't expect it, the linker script provides a link-time +check and fatal error message if the image size exceeds 128 KB. + diff --git a/board/cadence/xtfpga/lcd.c b/board/cadence/xtfpga/lcd.c new file mode 100644 index 0000000..4ea06bb --- /dev/null +++ b/board/cadence/xtfpga/lcd.c @@ -0,0 +1,88 @@ +/* + * Driver for the LCD display on the Tensilica XT-AV60 Board. + * + * Copyright (C) 2001 - 2013 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The LCD functions busy wait due to limitations of the LCD controller. + * This is a single-threaded boot-loader, so we don't care about that. + */ + + +#include <config.h> +#include <common.h> + +#define LCD_INSTR_ADDR (char *)(CONFIG_SYS_ASCDISP_ADDR + 0) +#define LCD_DATA_ADDR (char *)(CONFIG_SYS_ASCDISP_ADDR + 4) + +#define LCD_PAUSE_ITERATIONS 4000 +#define LCD_CLEAR 0x1 +#define LCD_DISPLAY_ON 0xc + +/* The KC704 requires 4-bit mode */ +#ifdef CONFIG_XTFPGA_KC705 +# define LCD_DISPLAY_FUNC 0x28 /* 4 bits and 2 lines display */ +# define LCD_DISPLAY_MODE 0x06 /* increase, not-shifted */ +#else +# define LCD_DISPLAY_FUNC 0x38 /* 8 bits and 2 lines display */ +# define LCD_DISPLAY_MODE 0x06 /* increase, not-shifted */ +#endif + +#define LCD_SHIFT_LEFT 0x18 +#define LCD_SHIFT_RIGHT 0x1c +#define LCD_DISPLAY_POS 0x80 + +#ifdef CONFIG_XTFPGA_KC705 +static inline void lcd_write(char *addr, char value) +{ + *addr = value; + udelay(500); + *addr = value << 4; + udelay(500); +} +#else +static inline void lcd_write(char *addr, char value) +{ + *addr = value; + udelay(500); +} +#endif + +void lcd_init(void) +{ + /* switching back to 8-bit mode needs at least 3 writes */ + *LCD_INSTR_ADDR = 0x33; + udelay(500); + *LCD_INSTR_ADDR = 0x33; + udelay(500); + *LCD_INSTR_ADDR = 0x33; + udelay(500); + *LCD_INSTR_ADDR = LCD_DISPLAY_FUNC; + udelay(500); + lcd_write(LCD_INSTR_ADDR, LCD_DISPLAY_FUNC); + lcd_write(LCD_INSTR_ADDR, LCD_DISPLAY_ON); + lcd_write(LCD_INSTR_ADDR, LCD_DISPLAY_MODE); + lcd_write(LCD_INSTR_ADDR, LCD_CLEAR); + udelay(2000); +} + +void lcd_disp_at_pos(char *str, char pos) +{ + lcd_write(LCD_INSTR_ADDR, LCD_DISPLAY_POS | pos); + udelay(100); + while (*str != 0) + lcd_write(LCD_DATA_ADDR, *str++); +} + +void lcd_shiftleft(void) +{ + lcd_write(LCD_INSTR_ADDR, LCD_SHIFT_LEFT); +} + +void lcd_shiftright(void) +{ + lcd_write(LCD_INSTR_ADDR, LCD_SHIFT_RIGHT); +} diff --git a/board/cadence/xtfpga/lcd.h b/board/cadence/xtfpga/lcd.h new file mode 100644 index 0000000..878b740 --- /dev/null +++ b/board/cadence/xtfpga/lcd.h @@ -0,0 +1,12 @@ +/* + * Driver for the LCD display on the Tensilica LX60 Board. + * + * Copyright (C) 2001 - 2013 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void lcd_init(void); +void lcd_disp_at_pos(char *, unsigned char); +void lcd_shiftleft(void); +void lcd_shiftright(void); diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c new file mode 100644 index 0000000..cf6eaf0 --- /dev/null +++ b/board/cadence/xtfpga/xtfpga.c @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2007 - 2013 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <linux/ctype.h> +#include <linux/string.h> +#include <linux/stringify.h> +#include <asm/xtensa.h> +#include <asm/global_data.h> +#include <netdev.h> + +#include "lcd.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Check board idendity. + * (Print information about the board to stdout.) + */ + + +#if defined(CONFIG_XTFPGA_LX60) +const char *board = "XT_AV60"; +const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; +#elif defined(CONFIG_XTFPGA_LX110) +const char *board = "XT_AV110"; +const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_LX200) +const char *board = "XT_AV200"; +const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_ML605) +const char *board = "XT_ML605"; +const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_KC705) +const char *board = "XT_KC705"; +const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / "; +#else +const char *board = "<unknown>"; +const char *description = ""; +#endif + +int checkboard(void) +{ + printf("Board: %s: %sTensilica bitstream\n", board, description); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +int board_postclk_init(void) +{ + /* + * Obtain CPU clock frequency from board and cache in global + * data structure (Hz). Return 0 on success (OK to continue), + * else non-zero (hang). + */ + +#ifdef CONFIG_SYS_FPGAREG_FREQ + gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#else + /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ + gd->cpu_clk = 50000000UL; +#endif + return 0; +} + +/* + * Miscellaneous early initializations. + * We use this hook to retrieve the processor frequency + * and to initialize the LCD display. + */ + +int misc_init_f(void) +{ +#ifdef CONFIG_SYS_ASCDISP + /* Initialize the LCD. */ + + lcd_init(); +#endif + display_printf("U-Boot starting", NULL); + + return 0; +} + +/* + * Miscellaneous late initializations. + * The environment has been set up, so we can set the Ethernet address. + */ + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_NET + /* + * Initialize ethernet environment variables and board info. + * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6. + */ + + char *s = getenv("ethaddr"); + if (s == 0) { + unsigned int x; + s = __stringify(CONFIG_ETHBASE); + x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + & FPGAREG_MAC_MASK; + sprintf(&s[15], "%02x", x); + setenv("ethaddr", s); + } +#endif /* CONFIG_CMD_NET */ + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + return ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE); +} +#endif + + +/* + * Print a formatted string to the board's ASCII character display. + * String may have embedded newlines. Starts at top left and wraps long lines. + */ + +#ifdef CONFIG_SYS_ASCDISP +void display_printf(const char *fmt, ...) +{ + va_list args; + + /* Warning: sprintf() can overflow this buffer if too small! */ + char buf[CONFIG_SYS_ASCDISP_BUFSZ]; + int i; + + va_start(args, fmt); + vsprintf(buf, fmt, args); + + /* Truncate to one line and pad line with blanks. */ + for (i = 0; + i < CONFIG_SYS_ASCDISP_BUFSZ-1 && buf[i] != '\0' && buf[i] != '\n'; + ++i) + ; + for (; i < CONFIG_SYS_ASCDISP_CHARS; ++i) + buf[i] = ' '; + buf[CONFIG_SYS_ASCDISP_CHARS] = 0; + + lcd_disp_at_pos(buf, 0); + + va_end(args); +} +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +/* Display a boot progress number on the LCD display. */ +void show_boot_progress(int val) +{ + display_printf("Progress = %d", val); +} +#endif + +/* Implement the "reset" command. */ +void board_reset(void) +{ + *(vu_long *)CONFIG_SYS_FPGAREG_RESET = CONFIG_SYS_FPGAREG_RESET_CODE; + /* Shouldn't reach here. */ +} diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig new file mode 100644 index 0000000..009ce35 --- /dev/null +++ b/configs/xtfpga_defconfig @@ -0,0 +1,3 @@ +CONFIG_XTENSA=y +CONFIG_SYS_CPU="dc232b" +CONFIG_XTFPGA_KC705=y diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h new file mode 100644 index 0000000..a932ea0 --- /dev/null +++ b/include/configs/xtfpga.h @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2007-2013 Tensilica, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/addrspace.h> + +/* + * The 'xtfpga' board describes a set of very similar boards with only minimal + * differences. Define one of the following in boards.cfg + * XTFPGA_LX60 + * XTFPGA_LX110 + * XTFPGA_LX200 + * XTFPGA_ML605 + * XTFPGA_KC705 + */ + +/*=====================*/ +/* Board and Processor */ +/*=====================*/ + +#define CONFIG_XTFPGA + +/* FPGA CPU freq after init */ +#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) + +/* Which (core) timer to use */ +#define CONFIG_TIMER_INDEX 0 +#define CONFIG_SYS_HZ 1000 /* timer-ticks/second */ + +/*===================*/ +/* RAM Memory Layout */ +/*===================*/ + +/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ +#ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128 << 10 */ +#else +# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256 << 10 */ +#endif + +#define CONFIG_SYS_STACKSIZE (512 << 10) /* stack 128KB */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ + +/* Linux boot param area in RAM (used only when booting linux) */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +/* U-Boot initial RAM area before it unpacks itself (not currently used) */ + +/* Memory test is destructive so default must not overlap vectors or U-Boot*/ +#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) +#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) + +/* Load address for stand-alone applications. + * MEMADDR cannot be used here, because the definition needs to be + * a plain number as it's used as -Ttext argument for ld in standalone + * example makefile. Handle MMUv2 vs MMUv3 distinction here manually. + */ +#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR +#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 +#else +#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 +#endif + +/* SDRAM sizes: */ +/* LX60 0x04000000 64 MB */ +/* LX110 0x03000000 48 MB */ +/* LX200 0x06000000 96 MB */ +/* ML605 0x20000000 512 MB */ +/* KC705 0x40000000 1 GB */ + +#define CONFIG_SYS_SDRAM_PHYS 0x00000000 +#define CONFIG_SYS_SDRAM_VADDR MEMADDR(0x00000000) +#ifndef CONFIG_SYS_MEMORY_SIZE +# define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE +#endif + +#define CONFIG_SYS_MEMORY_TOP \ + (CONFIG_SYS_MEMORY_BASE + CONFIG_SYS_MEMORY_SIZE) + +#define CONFIG_SYS_BOOTPARAMS_ADDR \ + (CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_BOOTPARAMS_LEN) +#define CONFIG_SYS_SP_TOP \ + (CONFIG_SYS_BOOTPARAMS_ADDR - GD_SIZE) +#define CONFIG_SYS_TEXT_ADDR \ + (CONFIG_SYS_SP_TOP - CONFIG_SYS_STACKSIZE - CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_SYS_GD_ADDR CONFIG_SYS_SP_TOP + +/* Used by tftpboot; env var 'loadaddr' */ +#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) + +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ + +#undef CONFIG_USE_IRQ /* Keep it simple, poll only */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MISC_INIT_R +#define CONFIG_MISC_INIT_F + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_SYS_PROMPT "U-Boot> " + /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 + /* Prt buf */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + /* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + + +/* Enable device tree support */ +#define CONFIG_OF_LIBFDT 1 +/*#define CONFIG_FIT*/ + +/*=================*/ +/* U-Boot commands */ +/*=================*/ + +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SAVEENV +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +/*==============================*/ +/* U-Boot autoboot configuration */ +/*==============================*/ + +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ +#define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */ +#define CONFIG_BOOT_RETRY_MIN 1 /* at least 1 second timeout */ +/* + * Be selective on what keys can delay or stop the autoboot process + * To stop use: " " + */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press <SPACE> to stop\n", bootdelay +#define CONFIG_AUTOBOOT_STOP_STR " " +#undef CONFIG_AUTOBOOT_DELAY_STR +#define DEBUG_BOOTKEYS 0 + +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_SHOW_BOOT_PROGRESS + +#ifdef DEBUG +#define CONFIG_PANIC_HANG 1 /* Require manual reboot */ +#endif + + +/*=========================================*/ +/* FPGA Registers (board info and control) */ +/*=========================================*/ + +/* + * These assume FPGA bitstreams from Tensilica release RB and up. Earlier + * releases may not provide any/all of these registers or at these offsets. + * Some of the FPGA registers are broken down into bitfields described by + * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. + */ + +/* Date of FPGA bitstream build in binary coded decimal (BCD) */ +#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) +#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ +#define FPGAREG_MTH_WIDTH 8 +#define FPGAREG_MTH_MASK 0xFF000000 +#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ +#define FPGAREG_DAY_WIDTH 8 +#define FPGAREG_DAY_MASK 0x00FF0000 +#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ +#define FPGAREG_YEAR_WIDTH 16 +#define FPGAREG_YEAR_MASK 0x0000FFFF + +/* FPGA core clock frequency in Hz (also input to UART) */ +#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ + +/* + * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): + * Bits 0..5 set the lower 6 bits of the default ethernet MAC. + * Bit 6 is reserved for future use by Tensilica. + * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * the base of flash * (when on/1) or to the base of RAM (when off/0). + */ +#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ +#define FPGAREG_MAC_WIDTH 6 +#define FPGAREG_MAC_MASK 0x3f +#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ +#define FPGAREG_BOOT_WIDTH 1 +#define FPGAREG_BOOT_MASK 0x80 +#define FPGAREG_BOOT_RAM 0 +#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) + +/* Force hard reset of board by writing a code to this register */ +#define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ +#define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ + +/*====================*/ +/* ASCII Display Info */ +/*====================*/ + +#ifndef CONFIG_XTFPGA_LX200 /* LX200 has no ascii display */ +# ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_ASCDISP_ADDR IOADDR(0x0D040000) +# else +# define CONFIG_SYS_ASCDISP_ADDR IOADDR(0x0D0C0000) +# endif +#define CONFIG_SYS_ASCDISP_LINES 2 +#define CONFIG_SYS_ASCDISP_CHARS 16 +#define CONFIG_SYS_ASCDISP_BUFSZ 64 /* Display printf buffer size */ +#endif + +/*====================*/ +/* Serial Driver Info */ +/*====================*/ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ + +/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_NS16550_BROKEN_TEMT + +/*======================*/ +/* Ethernet Driver Info */ +/*======================*/ + +#define CONFIG_ETHOC +#define CONFIG_ETHBASE 00:50:C2:13:6f:00 +#define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) +#define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) +#define CONFIG_SYS_ETHOC_SETUP_PHY + +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */ +#undef CONFIG_FLASH_CFI_LEGACY /* only use CFI for flash */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#ifdef CONFIG_XTFPGA_LX60 +# define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +#elif defined(CONFIG_XTFPGA_KC705) +# define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) +#else +# define CONFIG_SYS_FLASH_SIZE 0x0200000 /* 32MB */ +# define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ +# define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ +# define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) +#endif +#define CONFIG_SYS_MAX_FLASH_SECT \ + (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ + CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) +#define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */ + +#define CONFIG_SYS_FLASH_TOP (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) + +/* U-Boot monitor lives at the base of flash where it's mapped to ROM area */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +/* + * Put environment in top block (64kB) + * Another option would be to put env. in 2nd param block offs 8KB, size 8KB + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ) +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ + +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#endif /* __CONFIG_H */