The PLLADIV2 bit is not defined in at91sam9261 SoC, so remove it.
Signed-off-by: Bo Shen voice.shen@atmel.com
--- Changes in v4: - New Changes in v3: - None Changes in v2: - None
include/configs/pm9261.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index fc95cf0..acf6d61 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -50,15 +50,13 @@ #define CONFIG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2 | \ - AT91_PMC_MCKR_PLLADIV_1) + AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */ #define CONFIG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2 | \ - AT91_PMC_MCKR_PLLADIV_1) + AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000