Re: [PATCH v2 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

On Thu, 26 May 2022 at 07:38, Paweł Anikiel pan@semihalf.com wrote:

For some reason, on the Mercury+ AA1 module, calling fpgamgr_wait_early_user_mode immediately after writing the peripheral bitstream leaves the fpga in a broken state (ddr calibration hangs). Adding a delay before the first sync word is written seems to fix this. Inspecting the fpgamgr registers before and after the delay, imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit (instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel pan@semihalf.com

drivers/fpga/socfpga_arria10.c | 8 ++++++++ 1 file changed, 8 insertions(+)

Reviewed-by: Simon Glass sjg@chromium.org