From: Dinh Nguyen dinguyen@opensource.altera.com
Add miscellaneous functions(arch_early_init_r, print_cpuinfo, overwrite_console, enable_caches, and cpu_mmc_init). Also, the Arria10 has a firewall protection around the SDRAM and OCRAM. These firewalls are to be disabled in order for U-Boot to function.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/arria10/misc_a10.c | 138 +++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 arch/arm/mach-socfpga/arria10/misc_a10.c
diff --git a/arch/arm/mach-socfpga/arria10/misc_a10.c b/arch/arm/mach-socfpga/arria10/misc_a10.c new file mode 100644 index 0000000..f245bae --- /dev/null +++ b/arch/arm/mach-socfpga/arria10/misc_a10.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager_a10.h> +#include <asm/arch/sdram_a10.h> +#include <asm/arch/dwmmc.h> +#include <asm/pl310.h> +#include <altera.h> +#include <dwmmc.h> +#include <fpga.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct pl310_regs *pl310_regs_base = (void *)CONFIG_SYS_PL310_BASE; +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; + +/* FPGA programming support for SoC FPGA Arria 10 */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* add device descriptor to FPGA device table */ +static void socfpga_fpga_add(void) +{ + int i; + fpga_init(); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) + fpga_add(fpga_altera, &altera_fpga[i]); +} + +void v7_outer_cache_enable(void) +{ + /* disable the L2 cache */ + writel(0, &pl310_regs_base->pl310_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310_regs_base->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK); +} + +/* + * This function initializes security policies to be consistent across + * all logic units in the Arria 10. + * + * The idea is to set all security policies to be normal, nonsecure + * for all units. + */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f0000, &noc_fw_ocram_base->region0); + writel(0x1, &noc_fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr); + writel(0x1, &noc_fw_ddr_l3_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &pl310_regs_base->pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + reset_assert_all_peripherals_except_l4wd0_l4timer0(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Arria 10 Platform\n"); + return 0; +} +#endif + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ +defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_DWMMC +/* + * Initializes MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return socfpga_dwmmc_init(gd->fdt_blob); +} +#endif + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +}