From: Dinh Nguyen dinguyen@opensource.altera.com
Add code to handle status of the bsel.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 61 ++++++++++++---------- arch/arm/cpu/armv7/socfpga/spl.c | 2 + arch/arm/include/asm/arch-socfpga/reset_manager.h | 31 +++++++++++ arch/arm/include/asm/arch-socfpga/system_manager.h | 9 +++- 4 files changed, 73 insertions(+), 30 deletions(-)
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index f251f07..ee3c9fa 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -6,44 +6,49 @@
#include <config.h> #include <version.h> +#include <linux/linkage.h> +#include <asm-offsets.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h>
/* Save the parameter pass in by previous boot loader */ .global save_boot_params save_boot_params: /* no parameter to save */ - bx lr -
- /* Remap */ #ifdef CONFIG_SPL_BUILD /* - * SPL : configure the remap (L3 NIC-301 GPV) - * so the on-chip RAM at lower memory instead ROM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x19 - str r1, [r0] -#else - /* - * U-Boot : configure the remap (L3 NIC-301 GPV) - * so the SDRAM at lower memory instead on-chip RAM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x2 - str r1, [r0] + * If BSEL is zero, then the bootrom has not + * handed any information to preloader. + */ + ldr r9,=SYSMGR_BOOTINFO + ldr r9, [r9] + and r9, r9, #SYSMGR_BOOTINFO_BSEL_MASK + cmp r9, #0 + bne bsel_non_zero + ldr r4, =rst_mgr_status + ldr r5, =RSTMGR_COLDRST_MASK + str r5, [r4] + b bsel_zero
- /* Private components security */ +bsel_non_zero: + /* get the reset manager status register passed by BootROM */ + add r5, r0,#0x38 + ldr r4, =rst_mgr_status + ldr r5, [r5] + str r5, [r4]
+bsel_zero: /* - * U-Boot : configure private timer, global timer and cpu - * component access as non secure for kernel stage (as required - * by kernel) + * Initialize the early stack point on OCRAM. This is to avoid OCRAM + * false double bit error as OCRAM always ready in 64 bit manner */ - mrc p15,4,r0,c15,c0,0 - add r1, r0, #0x54 - ldr r2, [r1] - orr r2, r2, #0xff - orr r2, r2, #0xf00 - str r2, [r1] + ldr r1, =(CONFIG_SYS_INIT_SP_ADDR) /* start of temporary SP */ + sub r0, r1, #GD_SIZE /* start of mem init */ + mov r2, #0x00000000 /* prepare zero to mem init */ +clrsp: cmp r0, r1 /* while not at end of BSS */ + strlo r2, [r0] /* clear 32-bit BSS word */ + addlo r0, r0, #4 /* move to next */ + blo clrsp #endif /* #ifdef CONFIG_SPL_BUILD */ - mov pc, lr + bx lr diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 16ca8b0..bf5b682 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -20,6 +20,8 @@
DECLARE_GLOBAL_DATA_PTR;
+u32 rst_mgr_status; + #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index d63a285..9b3f279 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -7,6 +7,7 @@ #ifndef _RESET_MANAGER_H_ #define _RESET_MANAGER_H_
+#ifndef __ASSEMBLY__ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void);
@@ -29,6 +30,7 @@ struct socfpga_reset_manager { u32 per2_mod_reset; u32 brg_mod_reset; }; +#endif /* __ASSEMBLY__ */
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 @@ -45,4 +47,33 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_SPIM1_LSB 19 #define RSTMGR_PERMODRST_SDR_LSB 29
+#define RSTMGR_STAT_L4WD1RST_MASK 0x00008000 +#define RSTMGR_STAT_L4WD0RST_MASK 0x00004000 +#define RSTMGR_STAT_MPUWD1RST_MASK 0x00002000 +#define RSTMGR_STAT_MPUWD0RST_MASK 0x00001000 +#define RSTMGR_STAT_SWWARMRST_MASK 0x00000400 +#define RSTMGR_STAT_FPGAWARMRST_MASK 0x00000200 +#define RSTMGR_STAT_NRSTPINRST_MASK 0x00000100 +#define RSTMGR_STAT_SWCOLDRST_MASK 0x00000010 +#define RSTMGR_STAT_CONFIGIOCOLDRST_MASK 0x00000008 +#define RSTMGR_STAT_FPGACOLDRST_MASK 0x00000004 +#define RSTMGR_STAT_NPORPINRST_MASK 0x00000002 +#define RSTMGR_STAT_PORVOLTRST_MASK 0x00000001 + +#define RSTMGR_WARMRST_MASK (\ + RSTMGR_STAT_L4WD1RST_MASK | \ + RSTMGR_STAT_L4WD0RST_MASK | \ + RSTMGR_STAT_MPUWD1RST_MASK | \ + RSTMGR_STAT_MPUWD0RST_MASK | \ + RSTMGR_STAT_SWWARMRST_MASK | \ + RSTMGR_STAT_FPGAWARMRST_MASK | \ + RSTMGR_STAT_NRSTPINRST_MASK) +#define RSTMGR_COLDRST_MASK (\ + RSTMGR_STAT_SWCOLDRST_MASK | \ + RSTMGR_STAT_CONFIGIOCOLDRST_MASK | \ + RSTMGR_STAT_FPGACOLDRST_MASK | \ + RSTMGR_STAT_NPORPINRST_MASK | \ + RSTMGR_STAT_PORVOLTRST_MASK) + + #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 10659f7..01ce2e2 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -15,8 +15,6 @@ void sysmgr_enable_warmrstcfgio(void); /* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
-#endif - struct socfpga_system_manager { /* System Manager Module */ u32 siliconid1; /* 0x00 */ @@ -118,6 +116,8 @@ struct socfpga_system_manager { u32 spim0usefpga; /* 0x738 */ };
+#endif /* __ASSEMBLY__ */ + #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) #define SYSMGR_ECC_OCRAM_EN (1 << 0) @@ -154,4 +154,9 @@ struct socfpga_system_manager { */ #define SOCFPGA_MPUL2_ADRFLTR_START (0xC00)
+#define SYSMGR_BOOTINFO (SOCFPGA_SYSMGR_ADDRESS + 0x14) +#define SYSMGR_BOOTINFO_CSEL_LSB 3 +#define SYSMGR_BOOTINFO_CSEL_MASK 0x18 +#define SYSMGR_BOOTINFO_BSEL_MASK 0x7 + #endif /* _SYSTEM_MANAGER_H_ */