On Thu, 2014-06-26 at 02:25 -0600, Danny Gale wrote:
Hello everybody,
We're trying to boot a custom board loosely based on the T4240QDS. We have the T4240 coming up and getting its RCW / PBL from a SPI EEPROM, and it reads 8 KB of program from NAND flash into SRAM, then dies.
The T4240QDS_NAND target assumes that the PBL comes from NAND, not SPI EEPROM, and relies on the PBL to load the SPL into SRAM. The method you describe may be possible -- it's similar to how NAND boot was done prior to PBL -- but it will need some development work.
I think we just don't have things in the right places. I'm a little confused and have a couple of questions on addresses and what goes where:
- The SPL image itself should go at address 0 in the NAND flash,
correct? That's where our PowerPC will start to look for it.
The PBL-encoded SPL image should go at address 0 in NAND flash.
- The u-boot.bin image should be programmed to
CONFIG_SYS_NAND_U_BOOT_OFFS in the NAND flash, right? (pretty sure this is true -- just sanity-checking myself here)
Yes.
- How does CONFIG_SYS_TEXT_BASE relate to CONFIG_SYS_NAND_U_BOOT_DST
and CONFIG_SYS_NAND_U_BOOT_START? Why aren't all three of these the same?
They're related, but not necessarily the same. START can be greater than DST if the payload is not block-aligned (e.g. on mpc8313erdb) and/or if the image contains a non-executable header.
TEXT_BASE can be greater than START because it is the address of the beginning of the text section, which may not be the first executable section in the image. On e500 nand boot, the bootpg section comes first.
- What are RESET_VECTOR_OFFSET and BOOT_PAGE_OFFSET?
RESET_VECTOR_OFFSET is the offset into the SPL image of the reset vector, and BOOT_PAGE_OFFSET is the offset at which the bootpg section should be linked.
I've CCed Shaohui Xie who may be able to say more about how it works in PBL boot scenarios.
-Scott