Hi Ley,
On Mon, 6 Jan 2020 at 01:09, Ley Foon Tan ley.foon.tan@intel.com wrote:
In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue.
Retry with this fix more than 10 times without issue.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Remove _status callback and poll reset status after deassert reset
v2:
v1:
drivers/reset/reset-socfpga.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..172028dcf6 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -78,9 +78,20 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int reg_width = sizeof(u32); int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE);
int i = 1000;u32 status; clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
return 0;
/* Poll until reset is completed. */do {status = readl(data->modrst_base + (bank * BANK_INCREMENT)) &BIT(offset);if (!status)return 0;} while (i--);
This should be something like:
start = get_timer(0); while (1) { existing code if (get_timer(start) > TIMEOUT_MS) return -ETIMEOUT; };
so that you actually have a timeout. At present the timeout is indeterminate.
return -ETIMEDOUT;}
static int socfpga_reset_request(struct reset_ctl *reset_ctl)
2.19.0
Regards, Simon