Hi All,
I have been struggling for quite some time now to get SPL and u-boot to run from QSPI-flash. Yesterday I was able to identify a workaround to get the SPL going by disabling quad mode for the flash (seems identified by http://lists.denx.de/pipermail/u-boot/2016-June/256671.html). However u-boot always hangs after printing memory size. I have tried to search the archive and have seen posts about hanging here, but nothing I can relate to my setup. I have tested to use Altera's SPL (2013.01.01) and u-boot-2016.5 and this combo seems to work.
I also notice that the frequency (max-spi-frequency) in the dts-file is not picked up for some reason?
Any help to fix the u-boot hang problem would be highly appreciated.
Current printout (with added debug output):
U-Boot SPL 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from SPI spl_spi_load_image: bus=0, cs=0, speed=50000000, mode=3 cadence_spi_ofdata_to_platdata: regbase=ff705000 ahbbase=ffa00000 max-frequency=500000 page-size=256 spi_flash_std_probe: slave=01100368, cs=0 SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=100000 cadence_spi_xfer: len=1 [bytes] cadence_spi_xfer: len=5 [bytes] SF: Got idcodes 00000000: 20 ba 20 10 00 . .. SF: Detected N25Q512 cadence_spi_xfer: len=1 [bytes] cadence_spi_xfer: len=1 [bytes] spi_flash_decode_fdt: Cannot decode address cadence_spi_xfer: len=0 [bytes] cadence_spi_xfer: len=0 [bytes] SF: Detected N25Q512 with page size 256 Bytes, erase size 64 KiB, total 64 MiB SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=500000 cadence_spi_xfer: len=5 [bytes] cadence_spi_xfer: len=64 [bytes] cadence_spi_xfer: len=5 [bytes] cadence_spi_xfer: len=443714 [bytes]
U-Boot 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20 +0200)
CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: QSPI Flash (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB
Best regards,
Christian