Rename CONFIG_SYS_DDR_CONFIG to include which CS it is configuring Cleanup the setting of the csnbds to respect the setting of CONFIG_SYS_DDR_SDRAM_BASE Use __ilog2 instead of writing the code to compute it Disable unused CS configs Ensure ddrlaw.bar is configured
Signed-off-by: Joe Hershberger joe.hershberger@ni.com Cc: Joe Hershberger joe.hershberger@gmail.com Cc: Kim Phillips kim.phillips@freescale.com --- board/freescale/mpc8313erdb/sdram.c | 10 +++++- board/freescale/mpc8349emds/mpc8349emds.c | 27 +++++++++--------- board/freescale/mpc8349itx/mpc8349itx.c | 28 +++++++++++-------- board/freescale/mpc8360emds/mpc8360emds.c | 42 ++++++++++++++++++----------- board/sbc8349/sbc8349.c | 27 +++++++++--------- board/ve8313/ve8313.c | 10 +++++- include/configs/MPC8313ERDB.h | 2 +- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 2 +- include/configs/MPC8360EMDS.h | 7 +++-- include/configs/sbc8349.h | 2 +- include/configs/ve8313.h | 2 +- 12 files changed, 93 insertions(+), 68 deletions(-)
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 7aede13..a9a2ba4 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -74,8 +74,14 @@ static long fixed_sdram(void) */ __udelay(50000);
- im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 365ac37..edce4c3 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -97,18 +97,10 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(ddr_size); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
@@ -129,8 +121,15 @@ int fixed_sdram(void) im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 5647579..9cc808e 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -43,23 +43,27 @@ int fixed_sdram(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 ddr_size; /* The size of RAM, in bytes */ - u32 ddr_size_log2 = 0; - - for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { - if (ddr_size & 1) { - return -1; - } - ddr_size_log2++; - } + /* The size of RAM, in bytes */ + u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; + u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- /* Only one CS0 for DDR */ - im->ddr.csbnds[0].csbnds = 0x0000000f; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + + /* Only one CS for DDR */ + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 51d8035..a0114f6 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -216,19 +216,15 @@ phys_size_t initdram(int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); + u32 half_ddr_size = ddr_size >> 1; + + im->sysconf.ddrlaw[0].bar = + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif @@ -246,11 +242,25 @@ int fixed_sdram(void) im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[0].csbnds = 0x00000007; - im->ddr.csbnds[1].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; - im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.csbnds[1].csbnds = + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> + CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; + + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 50fae7c..42f4c1e 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -89,26 +89,25 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(msize); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 166e459..924d871 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -65,8 +65,14 @@ static long fixed_sdram(void) */ __udelay(50000);
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + out_be32(&im->ddr.csbnds[0].csbnds, + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA)); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
/* Currently we use only one CS, so disable the other bank. */ out_be32(&im->ddr.cs_config[1], 0); diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index a0ad225..624156a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -130,7 +130,7 @@ * seem to have the SPD connected to I2C. */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_RD_NEVER \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index c41ef31..c458060 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -126,7 +126,7 @@ #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_TIMING_1 0x36332321 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index d0586af..6506937 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -206,7 +206,7 @@ /* No SPD? Then manually set up DDR parameters */ #ifndef CONFIG_SPD_EEPROM #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ - #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ + #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10)
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 3a636ec..cce7515 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -145,9 +145,10 @@ #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e9eb632..a1377a4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -114,7 +114,7 @@ * NB: manual DDR setup untested on sbc834x */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ +#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_TIMING_1 0x36332321 diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 0cddca3..0c6c3a7 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -79,7 +79,7 @@ * have the SPD connected to I2C. */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_AP \ | CSCONFIG_ODT_RD_NEVER \ | CSCONFIG_ODT_WR_ALL \