This is an attempt to tidy up the early SPL code in an attempt to pave the way for driver model in SPL:
- Avoid setting up SDRAM before board_init_f() - Avoid touching global_data before board_init_f() - Allow board_init_f() to set up a new stack (seems that the SRAM stack is not large enough on these boards)
This needs more work but it does boot on Beaglebone Black.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/am33xx/board.c | 60 ++++++++++++++++++++++++++------------ arch/arm/cpu/armv7/lowlevel_init.S | 4 --- arch/arm/include/asm/spl.h | 3 ++ arch/arm/lib/crt0.S | 9 ++++++ include/configs/ti_armv7_common.h | 5 ++-- 5 files changed, 56 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 29b1d73..eeea81a 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -275,24 +275,11 @@ static void watchdog_disable(void) ; }
-void s_init(void) +static gd_t tmp_gdata __attribute__ ((section(".data"))); + +void board_init_f(ulong dummy) { - /* - * The ROM will only have set up sufficient pinmux to allow for the - * first 4KiB NOR to be read, we must finish doing what we know of - * the NOR mux in this space in order to continue. - */ -#ifdef CONFIG_NOR_BOOT - enable_norboot_pin_mux(); -#endif - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif + gd->arch.omap_boot_params = tmp_gdata.arch.omap_boot_params; watchdog_disable(); timer_init(); set_uart_mux_conf(); @@ -303,7 +290,6 @@ void s_init(void) serial_init(); gd->have_console = 1; #elif defined(CONFIG_SPL_BUILD) - gd = &gdata; preloader_console_init(); #endif #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) @@ -314,5 +300,43 @@ void s_init(void) board_early_init_f(); sdram_init(); #endif + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); +#ifdef CONFIG_SPL_STACK_R + unsigned long start_addr_sp; + + start_addr_sp = CONFIG_SPL_STACK_R - sizeof(gd_t); + /* 8-byte alignment for ARM ABI compliance */ + start_addr_sp &= ~0x07; + memcpy((void *)start_addr_sp, (void *)gd, sizeof(gd_t)); + spl_call_board_init_r(start_addr_sp, dummy, board_init_r); +#else + board_init_r(NULL, 0); +#endif +} + +void s_init(void) +{ + gd_t *old_gd; + + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + enable_norboot_pin_mux(); +#endif + old_gd = (gd_t *)gd; + gd = &tmp_gdata; + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#ifdef CONFIG_SPL_BUILD + save_omap_boot_params(); +#endif + gd = &old_gd; } #endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index f1aea05..e294db9 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -21,13 +21,9 @@ ENTRY(lowlevel_init) */ ldr sp, =CONFIG_SYS_INIT_SP_ADDR bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#ifdef CONFIG_SPL_BUILD - ldr r9, =gdata -#else sub sp, sp, #GD_SIZE bic sp, sp, #7 mov r9, sp -#endif /* * Save the old lr(passed in ip) and the current lr to stack */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 8acd7cd..66d983a 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -35,4 +35,7 @@ extern char __bss_start[], __bss_end[];
extern gd_t gdata;
+void spl_call_board_init_r(ulong start_addr_sp, ulong boot_flags, + void (*board_init_r)(gd_t *new_gd, ulong dest_addr)); + #endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 22df3e5..be25fde 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -138,3 +138,12 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ #endif
ENDPROC(_main) + +/* + * spl_call_board_init_r(start_addr_sp, dummy, board_init_r) + */ +ENTRY(spl_call_board_init_r) + mov sp, r0 + mov r9, r0 + bx r2 +ENDPROC(spl_call_board_init_r) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index bc75172..38c0e63 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -76,8 +76,7 @@ #define CONFIG_NR_DRAM_BANKS 1 #endif #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR NON_SECURE_SRAM_END
/* Timer information. */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ @@ -214,7 +213,7 @@ * end of the BSS area. We place our stack at 32MiB after the start of * DRAM to allow room for all of the above. */ -#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20)) +#define CONFIG_SPL_STACK_R (CONFIG_SYS_SDRAM_BASE + (32 << 20)) #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 #endif