
7 Mar
2016
7 Mar
'16
3:28 a.m.
At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/dts/chromebook_link.dts | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 12f315e..a702ea9 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -74,6 +74,8 @@ northbridge@0,0 { reg = <0x00000000 0 0 0 0>; compatible = "intel,bd82x6x-northbridge"; + board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>, + <&gpio_b 11 0>, <&gpio_a 10 0>; u-boot,dm-pre-reloc; spd { compatible = "memory-spd";
--
2.7.0.rc3.207.g0ac5344