This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3.
This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks.
Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- This patch supersedes http://patchwork.ozlabs.org/patch/177408/ . Changes for v2: - Consequences from the previous cleanup patches. - Add detailed description.
.../arch/arm/cpu/armv7/mx5/clock.c | 36 +++++++++++++------- 1 file changed, 24 insertions(+), 12 deletions(-)
diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c index c7a3c36..40de128 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/armv7/mx5/clock.c +++ u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c @@ -326,28 +326,40 @@ static u32 get_ipg_per_clk(void) return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); }
-/* - * Get the rate of uart clk. - */ -static u32 get_uart_clk(void) +/* Get the output clock rate of a standard PLL MUX for peripherals. */ +static u32 get_standard_pll_sel_clk(u32 clk_sel) { - unsigned int freq, reg, pred, podf; + u32 freq;
- reg = readl(&mxc_ccm->cscmr1); - switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) { - case 0x0: + switch (clk_sel & 0x3) { + case 0: freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); break; - case 0x1: + case 1: freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); break; - case 0x2: + case 2: freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); break; - default: - return 66500000; + case 3: + freq = get_lp_apm(); + break; }
+ return freq; +} + +/* + * Get the rate of uart clk. + */ +static u32 get_uart_clk(void) +{ + unsigned int clk_sel, freq, reg, pred, podf; + + reg = readl(&mxc_ccm->cscmr1); + clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); + freq = get_standard_pll_sel_clk(clk_sel); + reg = readl(&mxc_ccm->cscdr1); pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg); podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);