Maximum CPU clock of R8A7790 that are used in lager board is 1.4GHz. This change to use the maximum clock in this board.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com --- board/renesas/lager/lager.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 959f46a..898fb57 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -24,15 +24,21 @@
DECLARE_GLOBAL_DATA_PTR;
+#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc;
/* Watchdog init */ writel(0xA5A5A500, &rwdt->rwtcsra); writel(0xA5A5A500, &swdt->swtcsra);
+ /* CPU frequency setting. Set to 1.4GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + /* QoS(Quality-of-Service) Init */ qos_init(); }