Add support for USB-A9263 board manufactured by Calao Systems (http://www.calao-systems.com/). Code is based on old U-Boot sources (2010.09) released by Calao.
Signed-off-by: Mateusz Kulikowski mateusz.kulikowski@gmail.com --- Changes for v3 - Updated Makefile to a new build system - Use generic GPIO for NAND and MAC (requires new GPIO patches) - Use common at91 phy reset - Dropped spi0 clock setup (pin is unused) - Fixed PHY address as 0x0001 and dropped PHY autodetect (no need for autodetect - PHY address is bootstrapped to 1) --- board/calao/usb_a9263/Makefile | 14 ++++ board/calao/usb_a9263/usb_a9263.c | 148 +++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/usb_a9263.h | 169 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 332 insertions(+) create mode 100644 board/calao/usb_a9263/Makefile create mode 100644 board/calao/usb_a9263/usb_a9263.c create mode 100644 include/configs/usb_a9263.h
diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile new file mode 100644 index 0000000..8a22b3e --- /dev/null +++ b/board/calao/usb_a9263/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian@popies.net +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2013 +# Mateusz Kulikowski mateusz.kulikowski@gmail.com +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += usb_a9263.o diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c new file mode 100644 index 0000000..266e950 --- /dev/null +++ b/board/calao/usb_a9263/usb_a9263.c @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, thomas.petazzoni@free-electrons.com + * Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm-generic/gpio.h> +#include <asm/io.h> +#include <net.h> +#include <netdev.h> +#include <dataflash.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HAS_DATAFLASH +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"}, +}; +#endif + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer); + + /* Configure RDY/BSY */ + gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + + /* Enable NandFlash */ + gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable"); + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal weak pull-up/pull-down + */ + gpio_request(GPIO_PIN_PC(25), "PHY mode"); + gpio_direction_input(GPIO_PIN_PC(25)); + + gpio_request(GPIO_PIN_PE(25), "PHY ADDR0"); + gpio_direction_input(GPIO_PIN_PE(25)); + + gpio_request(GPIO_PIN_PE(26), "PHY ADDR1"); + gpio_direction_input(GPIO_PIN_PE(26)); + + at91_phy_reset(); + + /* It will set proper pinmux for ports PC25, PE25-26 */ + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001); +#endif + return rc; +} diff --git a/boards.cfg b/boards.cfg index 36f0924..0f14fbb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -119,6 +119,7 @@ Active arm arm926ejs at91 calao tny_a9260 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre albin.tonnerre@free-electrons.com Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre albin.tonnerre@free-electrons.com Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre albin.tonnerre@free-electrons.com +Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski mateusz.kulikowski@gmail.com Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH info@egnite.de Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer reinhard.meyer@emk-elektronik.de Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer reinhard.meyer@emk-elektronik.de diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h new file mode 100644 index 0000000..c4d04de --- /dev/null +++ b/include/configs/usb_a9263.h @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2007-2013 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, thomas.petazzoni@free-electrons.com + * Mateusz Kulikowski mateusz.kulikowski@gmail.com + * + * Settings for Calao USB-A9263 board + * + * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap + * installed on board will not be able to load it properly. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/hardware.h> + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* + * Hardware drivers + */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +#endif + +#define MTDPARTS_DEFAULT \ + "mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)" + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=" MTDPARTS_DEFAULT " " \ + "rw rootfstype=jffs2" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +#endif