Re: [U-Boot] [Patch v4 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

On Mar 2, 2011, at 4:24 PM, York Sun wrote:

The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers.

Signed-off-by: York Sun yorksun@freescale.com

arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-)

applied to 8xxx

- k