Hi Marek,
On 09.11.2015 14:49, Marek Vasut wrote:
<snip>
--- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -73,7 +73,6 @@
/*
* Cache */-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
I hate to say it, but I am running into issues with this patch :-(
I'm sorry to hear this.
I use a standard USB stick here and with this patch, I am getting the following failure (with enabled and disabled cache):
=> usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... unable to get descriptor, error 0 usb_new_device: Cannot read configuration, skipping device 058f:6387 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found=> dcache off => usb reset resetting USB... USB0: Core Release: 2.93a scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) foundIf I revert this patch, my USB stick works as well.
I am also aware that Stefan mentions that without this patch, cache is not enabled at all. On the other hand, I cannot find any obviously faulty behavior in the dwc2 driver, it does flush_dcache_range()/invalidate_dcache_range() in the right places.
Any ideas please ?
Perhaps its a timing related issue? As the code is executed faster with cache enabled. Just an idea - perhaps there is still some ugly code that doesn't do proper timer based loops / delays.
I doubt that's not the case. If I disable cache just around the hcdma bit in the driver (disable before the flush_dcache_range() and enable after invalidate_dcache_range() in the driver), it still fails.
Did you check if this problem is perhaps also related to Dinh's L2 cache patch:
8d8e13e1 arm: socfpga: enable data/inst prefetch and shared override in the L2
?
I just noticed, that here the L2 cache gets disabled and is not enabled again in function v7_outer_cache_enable(). This looks a bit suspicious.
Dinh, did you perhaps miss to re-enable the L2 cache after the aux_ctrl register setup again?
Thanks, Stefan