From: Ying Zhang b40530@freescale.com
TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot.
Signed-off-by: Ying Zhang b40530@freescale.com --- Change from v6: - Delete the file "board/freescale/p1022ds/tpl.c". - Reuse the file "board/freescale/p1022ds/spl.c" in the TPL. Change from v5: - Change functionality nand_load_image to nand_load, it is called in TPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL".
board/freescale/p1022ds/spl.c | 15 +++++++ board/freescale/p1022ds/spl_minimal.c | 53 ++----------------------- include/configs/P1022DS.h | 69 ++++++++++++++++++++++++++------ 3 files changed, 76 insertions(+), 61 deletions(-)
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index b6669f3..79e3ac4 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -101,21 +101,36 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, \ CONFIG_SPL_RELOC_MALLOC_SIZE); +#ifndef CONFIG_SPL_NAND_BOOT env_init(); +#endif #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); #endif /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else env_relocate(); +#endif
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else puts("Second program loader running in sram...\n"); +#endif
#ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); #endif } diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index 8d12fa6..efb2af3 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -27,51 +27,6 @@ #include <asm/fsl_ddr_sdram.h>
-/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -void sdram_init(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, - &ddr->sdram_cfg); - - in_be32(&ddr->sdram_cfg); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - in_be32(&ddr->sdram_cfg); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} - const static u32 sysclk_tbl[] = { 66666000, 7499900, 83332500, 8999900, 99999000, 11111000, 12499800, 13333200 @@ -83,6 +38,10 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif /* for FPGA */ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); @@ -98,9 +57,6 @@ void board_init_f(ulong bootflag)
puts("\nNAND boot... ");
- /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -111,6 +67,7 @@ void board_init_f(ulong bootflag)
void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); }
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 607b754..bb05dcb 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -81,22 +81,41 @@
#ifdef CONFIG_NAND #define CONFIG_SPL +#define CONFIG_TPL +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_COMMON_INIT_DDR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_MAX_SIZE (128 << 10) +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_TEXT_BASE 0x00201000 -#define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#define CONFIG_SPL_TEXT_BASE 0xff800000 +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) +#endif +#define CONFIG_SPL_PAD_TO 0x20000 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif
/* High Level Configuration Options */ @@ -351,6 +370,25 @@ #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) +#elif defined(CONFIG_NAND) +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) +#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) +#else +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (256 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) +#endif #endif #endif
@@ -600,8 +638,13 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND +#ifdef CONFIG_TPL_BUILD +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */