On 19/01/2013 20:09, Eric Nelson wrote:
Or even a different memory configuration. For example, this line in the updated mx6q_4x_mt41j128.cfg file sets a value of 0x831A0000 to the MMDC_MDCTL register for Quad/Dual or Dual-Lite devices, but a value of 0x83190000 on Solo-Lite.
Right - this is not strictly related to i.MX6, and we have also in the past, for example when different revisions of the same board have different memory chips, and different cfg files were used.
In English, this sets up a 64-bit memory bus except on Solo-Lite. Since designs like ours do allow the use of a 32-bit bus on a Quad Core machine, trying to represent all of the choices in a single file doesn't scale.
WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
Right
The concept here is that the processors use a different internal base address, and depending on this address, the macro does its work, writing on the selected address. But again, IMHO it is tricky, and it is strictly bound to i.MX6 when imximage is thought for all i.MX processors.
Let's say, instead of it, I prefer the solution using the preprocessor or as you suggest, using different .cfg files for the memory configurations.
Yep. We'll proceed with the separate file approach.
Nice, I will wait for your patches !
Best regards, Stefano Babic