10 Mar
2006
10 Mar
'06
9:41 a.m.
In message 47F3F98010FF784EBEE6526EAAB078D1C060A6@tq-mailsrv.tq-net.de you wrote:
Um, in my opinion the patch does a runtime check of the cpu revision, only the written value is dependent on the configured CAS latency.
Configured where?
+#if defined(DDR_CASLAT_20)
I can't find any definition or use of DDR_CASLAT_20 anywhere in U-Boot...
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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