Greentime Hu green.hu@gmail.com 於 2018年10月31日 週三 上午11:48寫道：
Rick Chen rickchen36@gmail.com 於 2018年10月29日 週一 上午10:25寫道：
Auer, Lukas lukas.auer@aisec.fraunhofer.de 於 2018年10月27日 週六 上午12:27寫道：
Hi Rick,
On Mon, 2018-10-22 at 09:39 +0800, Rick Chen wrote:
From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] Sent: Saturday, October 20, 2018 6:08 AM To: u-boot@lists.denx.de Cc: Bin Meng; Lukas Auer; Greentime Hu; Alexander Graf; Rick Jian- Zhi Chen(陳建志) Subject: [PATCH 18/30] riscv: invalidate the instruction cache before jumping to Linux
Signed-off-by: Lukas Auer lukas.auer@aisec.fraunhofer.de
arch/riscv/lib/bootm.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index a7a9fb921b..bc1d4b2864 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -38,6 +38,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) return 1;
kernel = (void (*)(ulong, void *))images->ep;
invalidate_icache_all();Hi Likas
I wull use cleanup_before_linux() which is in cpu.c as below
I would prefer to keep the invalidate_icache_all() in bootm.c since it is important in the context of the function. I do agree that the data and instruction caches should be disabled in cleanup_before_linux().
Hi Lukas
It is ok to keep the invalidate_icache_all() in bootm.c
Rick
Hi Rick,
Since cleanup_before_linux() will invalidate icache, I think it will be better to do the whole cache operations there. As we can see the document from ARM(doc/README.arm-caches) it also said that " Cleanup Before Linux:
- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and disable MMU and caches.
" This may reduce the redundant codes/cost. What do you think?
Hi Greentime
I agree with you. We shall consider to reduce the redundant codes/cost.
Hi Lukas
Can you drop this patch ? And move it to cache_flush() ?
Thought this patch have implement it. [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]
But I will send v2 patch to separate /riscv/lib/cache.c to /riscv/cpu/ax25/cache.c and /riscv/cpu/qemu/cache.c
After that you can implement it in /riscv/cpu/qemu/cache.c
Rick