Hi Haijun,
On Dec 11, 2013, at 7:35 AM, Haijun Zhang wrote:
The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width.
Signed-off-by: Haijun Zhang haijun.zhang@freescale.com
changs for V2:
- No changes
drivers/mmc/fsl_esdhc.c | 5 +++++ include/configs/T4240QDS.h | 1 + 2 files changed, 6 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b3b5f37..a5fee3c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -646,6 +646,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->host_caps &= ~MMC_MODE_4BIT; }
- /* Detect if the upper 4 pins are used for ESDHC */
+#if defined(CONFIG_T4240QDS)
- if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
mmc->host_caps &= ~MMC_MODE_8BIT;+#endif
Same comment applies as for the card detect quirk,
#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK etc.
if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 955e6b9..4799d38 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BRDCFG5 0x55 #define QIXIS_MUX_SDHC 2 +#define QIXIS_MUX_SDHC_WIDTH8 1 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
1.8.4.1
Regards
-- Pantelis