4 Nov
2016
4 Nov
'16
9:58 p.m.
On 11/03/2016 01:19 PM, Phil Edworthy wrote:
With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz.
This change fixes the calculation.
Signed-off-by: Phil Edworthy phil.edworthy@renesas.com
v2:
- Use the DIV_ROUND_UP macro
Acked-by: Marek Vasut marex@denx.de
--
Best regards,
Marek Vasut