On 12/26/2017 02:44 PM, Eugeniy Paltsev wrote:
Add option to set spi controller clock frequency via device tree using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API and implement dw_spi_get_clk their own way in their clock manager.
Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead)
Signed-off-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com
drivers/spi/designware_spi.c | 45 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5aa507b..9883841 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,6 +11,7 @@ */
#include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -18,7 +19,6 @@ #include <fdtdec.h> #include <linux/compat.h> #include <asm/io.h> -#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -94,6 +94,8 @@ struct dw_spi_priv { void __iomem *regs; unsigned int freq; /* Default frequency */ unsigned int mode;
struct clk clk;
unsigned long bus_clk_rate;
int bits_per_word; u8 cs; /* chip select pin */
@@ -176,14 +178,53 @@ static void spi_hw_init(struct dw_spi_priv *priv) debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); }
+/*
- We define dw_spi_get_clk function as 'weak' as some targets
- (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
^^^ '--- don't Besides that
Reviewed-by: Marek Vasut marex@denx.de
this should be applied after 2018.01 is out.