Dear York Sun,
In message 1363973369-26110-20-git-send-email-yorksun@freescale.com you wrote:
From: Liu Gang Gang.Liu@freescale.com
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
- Set the boot location to one PCIE or SRIO interface by RCW.
- Set a specific TLB entry for the boot process.
- Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
- Set a specific TLB entry in order to fetch ucode and ENV from master.
- Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV.
- Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang Gang.Liu@freescale.com
arch/powerpc/include/asm/immap_85xx.h | 1 + board/freescale/t4qds/tlb.c | 19 ++++++++++++++++++ boards.cfg | 2 ++ include/configs/t4qds.h | 34 ++++++++++++++++++++++++++------- 4 files changed, 49 insertions(+), 7 deletions(-)
CHECK: Alignment should match open parenthesis #157: FILE: board/freescale/t4qds/tlb.c:64: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
CHECK: Alignment should match open parenthesis #173: FILE: board/freescale/t4qds/tlb.c:148: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
Best regards,
Wolfgang Denk