The common code used to bring up secondary cores requires a final jump location to be stored in some sort of memory location, define this memory location to be the start of OCRAM, since it is available.
Signed-off-by: Marek Vasut marex@denx.de --- Cc: "Ariel D'Alessandro" ariel.dalessandro@collabora.com Cc: "NXP i.MX U-Boot Team" uboot-imx@nxp.com Cc: "Ying-Chun Liu (PaulLiu)" paul.liu@linaro.org Cc: Adam Ford aford173@gmail.com Cc: Andrejs Cainikovs andrejs.cainikovs@toradex.com Cc: Fabio Estevam festevam@gmail.com Cc: Manoj Sai abbaraju.manojsai@amarulasolutions.com Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Cc: Michael Trimarchi michael@amarulasolutions.com Cc: Peng Fan peng.fan@nxp.com Cc: Ricardo Salveti ricardo@foundries.io Cc: Simon Glass sjg@chromium.org Cc: Stefano Babic sbabic@denx.de Cc: Tim Harvey tharvey@gateworks.com Cc: Ye Li ye.li@nxp.com --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index cfd5479cd73..3034d280cc3 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -91,6 +91,10 @@ #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 #define FEC_QUIRK_ENET_MAC
+#ifdef CONFIG_ARMV8_PSCI /* Final jump location */ +#define CPU_RELEASE_ADDR 0x900000 +#endif + #define CAAM_ARB_BASE_ADDR (0x00100000) #define CAAM_ARB_END_ADDR (0x00107FFF) #define CAAM_IPS_BASE_ADDR (0x30900000)