This patch adds basic support for the Marvell DB-78460-BP evaulation board. This is the first board that uses the recently created Armada XP 78460 SoC support.
Signed-off-by: Stefan Roese sr@denx.de ---
board/Marvell/db-78460-bp/Makefile | 7 ++ board/Marvell/db-78460-bp/db-78460-bp.c | 120 ++++++++++++++++++++++++++++++++ board/Marvell/db-78460-bp/kwbimage.cfg | 12 ++++ boards.cfg | 1 + include/configs/db-78460-bp.h | 67 ++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 board/Marvell/db-78460-bp/Makefile create mode 100644 board/Marvell/db-78460-bp/db-78460-bp.c create mode 100644 board/Marvell/db-78460-bp/kwbimage.cfg create mode 100644 include/configs/db-78460-bp.h
diff --git a/board/Marvell/db-78460-bp/Makefile b/board/Marvell/db-78460-bp/Makefile new file mode 100644 index 0000000..c7006d0 --- /dev/null +++ b/board/Marvell/db-78460-bp/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2014 Stefan Roese sr@denx.de +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-78460-bp.o diff --git a/board/Marvell/db-78460-bp/db-78460-bp.c b/board/Marvell/db-78460-bp/db-78460-bp.c new file mode 100644 index 0000000..369b3a8 --- /dev/null +++ b/board/Marvell/db-78460-bp/db-78460-bp.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT(nr) (1UL << (nr)) + +#define ETH_PHY_CTRL_REG 0 +#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 +#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka + * "RD-AXP-GP rev 1.0". + * + * GPPs + * MPP# NAME IN/OUT + * ---------------------------------------------- + * 21 SW_Reset_ OUT + * 25 Phy_Int# IN + * 28 SDI_WP IN + * 29 SDI_Status IN + * 54-61 On GPP Connector ? + * 62 Switch Interrupt IN + * 63-65 Reserved from SW Board ? + * 66 SW_BRD connected IN + */ +#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20))) +#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27))) +#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0)) + +#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20)) +#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27)) +#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x00000000, MVEBU_MPP_BASE + 0x04); + writel(0x33000000, MVEBU_MPP_BASE + 0x08); + writel(0x11000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11111111, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000003, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-78460-BP\n"); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1545 PHY */ +void reset_phy(void) +{ + u16 devadr = CONFIG_PHY_BASE_ADDR; + char *name = "neta0"; + u16 reg; + + if (miiphy_set_current_dev(name)) + return; + + /* Enable QSGMII AN */ + /* Set page to 4 */ + miiphy_write(name, devadr, 0x16, 4); + /* Enable AN */ + miiphy_write(name, devadr, 0x0, 0x1140); + /* Set page to 0 */ + miiphy_write(name, devadr, 0x16, 0); + + /* Phy C_ANEG */ + miiphy_read(name, devadr, 0x4, ®); + reg |= 0x1E0; + miiphy_write(name, devadr, 0x4, reg); + + /* Soft-Reset */ + miiphy_write(name, devadr, 22, 0x0000); + miiphy_write(name, devadr, 0, 0x9140); + + /* Power up the phy */ + miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®); + reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK); + miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg); + + printf("88E1545 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/db-78460-bp/kwbimage.cfg b/board/Marvell/db-78460-bp/kwbimage.cfg new file mode 100644 index 0000000..719145f --- /dev/null +++ b/board/Marvell/db-78460-bp/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese sr@denx.de +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-78460-bp/binary.0 0000005b 00000068 diff --git a/boards.cfg b/boards.cfg index 947f2bc..a94b225 100644 --- a/boards.cfg +++ b/boards.cfg @@ -247,6 +247,7 @@ Active arm arm946es - armltd integrator Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel matt.waddel@linaro.org Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel matt.waddel@linaro.org +Active arm armv7 armada-xp Marvell - db-78460-bp - Stefan Roese sr@denx.de Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier hannes.petermaier@br-automation.com Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier hannes.petermaier@br-automation.com Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier hannes.petermaier@br-automation.com diff --git a/include/configs/db-78460-bp.h b/include/configs/db-78460-bp.h new file mode 100644 index 0000000..ae48655 --- /dev/null +++ b/include/configs/db-78460-bp.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2014 Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_78460_BP_H +#define _CONFIG_DB_78460_BP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_BASE_ADDR 0x10 +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +#define CONFIG_RESET_PHY_R + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_78460_BP_H */