Hi Andy,
This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com Signed-off-by: Andy Fleming afleming@freescale.com
[...]
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c new file mode 100644 index 0000000..3239171 --- /dev/null +++ b/drivers/net/fsl_mdio.c @@ -0,0 +1,117 @@ +/*
- Copyright 2009-2010 Freescale Semiconductor, Inc.
- Jun-jie Zhang b18070@freescale.com
- Mingkai Hu Mingkai.hu@freescale.com
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <miiphy.h> +#include <phy.h> +#include <fsl_mdio.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/fsl_enet.h>
+void tsec_local_mdio_write(tsec_mii_t *phyregs, int port_addr,
int dev_addr, int regnum, int value)+{
- int timeout = 1000000;
- out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
- out_be32(&phyregs->miimcon, value);
- asm("sync");
- while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--);
Semicolon needs to be on its own line.
+}
+int tsec_local_mdio_read(tsec_mii_t *phyregs, int port_addr,
int dev_addr, int regnum)+{
- int value;
- int timeout = 1000000;
- /* Put the address of the phy, and the register
* number into MIIMADD */- out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
- /* Clear the command register, and wait */
- out_be32(&phyregs->miimcom, 0);
- asm("sync");
- /* Initiate a read command, and wait */
- out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
- asm("sync");
- /* Wait for the the indication that the read is done */
- while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
&& timeout--);
dito.
Other than that this also looks good, so once my concerns are addressed:
Acked-by: Detlev Zundel dzu@denx.de
Cheers Detlev