Hi Marek,
Thank you for the patch.
On Wed, Apr 28, 2021 at 8:32 PM Marek Vasut marek.vasut@gmail.com wrote:
From: Hai Pham hai.pham.ud@renesas.com
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham hai.pham.ud@renesas.com Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com
drivers/clk/renesas/clk-rcar-gen3.c | 9 +++++ drivers/clk/renesas/renesas-cpg-mssr.c | 49 ++---------------------- drivers/clk/renesas/renesas-cpg-mssr.h | 52 ++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 45 deletions(-)
Tested on RZ/G2{EHMN} board
Tested-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com
Cheers, Prabhaka
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 27939d6318..49ab9134af 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -389,6 +389,15 @@ int gen3_clk_probe(struct udevice *dev)
priv->sscg = !(cpg_mode & BIT(12));
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {priv->info->status_regs = mstpsr;priv->info->control_regs = smstpcr;priv->info->reset_regs = srcr;priv->info->reset_clear_regs = srstclr;} else {return -EINVAL;}ret = clk_get_by_name(dev, "extal", &priv->clk_extal); if (ret < 0) return ret;diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 0cf80a9866..b1cf7f599c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
-/*
- Module Standby and Software Reset register offets.
- If the registers exist, these are valid for SH-Mobile, R-Mobile,
- R-Car Gen2, R-Car Gen3, and RZ/G1.
- These are NOT valid for R-Car Gen1 and RZ/A1!
- */
-/*
- Module Stop Status Register offsets
- */
-static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,0x9A0, 0x9A4, 0x9A8, 0x9AC,-};
-#define MSTPSR(i) mstpsr[i]
-/*
- System Module Stop Control Register offsets
- */
-static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,0x990, 0x994, 0x998, 0x99C,-};
-#define SMSTPCR(i) smstpcr[i]
-/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
-/* Modem Module Stop Control Register offsets (r8a73a4) */ -#define MMSTPCR(i) (smstpcr[i] + 0x20)
-/* Software Reset Clearing Register offsets */ -#define SRSTCLR(i) (0x940 + (i) * 4)
bool renesas_clk_is_mod(struct clk *clk) { return (clk->id >> 16) == CPG_MOD; @@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
clrbits_le32(base + SMSTPCR(reg), bitmask);return wait_for_bit_le32(base + MSTPSR(reg),
clrbits_le32(base + info->control_regs[reg], bitmask);return wait_for_bit_le32(base + info->status_regs[reg], bitmask, 0, 100, 0); } else {
setbits_le32(base + SMSTPCR(reg), bitmask);
setbits_le32(base + info->control_regs[reg], bitmask); return 0; }} @@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
/* Stop module clock */ for (i = 0; i < info->mstp_table_size; i++) {
clrsetbits_le32(base + SMSTPCR(i),
clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); clrsetbits_le32(base + RMSTPCR(i),diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 3c3b128c4c..92421b15ee 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -37,6 +37,10 @@ struct cpg_mssr_info { unsigned int clk_extal_usb_id; unsigned int pll0_div; const void *(*get_pll_config)(const u32 cpg_mode);
const u16 *status_regs;const u16 *control_regs;const u16 *reset_regs;const u16 *reset_clear_regs;};
/* @@ -125,4 +129,52 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, struct cpg_mssr_info *info, bool enable); int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+/*
- Module Standby and Software Reset register offets.
- If the registers exist, these are valid for SH-Mobile, R-Mobile,
- R-Car Gen2, R-Car Gen3, and RZ/G1.
- These are NOT valid for R-Car Gen1 and RZ/A1!
- */
+/*
- Module Stop Status Register offsets
- */
+static const u16 mstpsr[] = {
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,0x9A0, 0x9A4, 0x9A8, 0x9AC,+};
+/*
- System Module Stop Control Register offsets
- */
+static const u16 smstpcr[] = {
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,0x990, 0x994, 0x998, 0x99C,+};
+/*
- Software Reset Register offsets
- */
+static const u16 srcr[] = {
0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,0x920, 0x924, 0x928, 0x92C,+};
+/* Realtime Module Stop Control Register offsets */ +#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
+/* Modem Module Stop Control Register offsets (r8a73a4) */ +#define MMSTPCR(i) (smstpcr[i] + 0x20)
+/* Software Reset Clearing Register offsets */
+static const u16 srstclr[] = {
0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,0x960, 0x964, 0x968, 0x96C,+};
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
2.30.2