With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM.
Introduce a new SPL_SMP Kconfig option to support this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Atish Patra atish.patra@wdc.com ---
Changes in v2: None
arch/riscv/Kconfig | 13 ++++++++++++- arch/riscv/cpu/start.S | 14 +++++++------- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 2 +- 6 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3061bf8..5ef6849 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -200,10 +200,21 @@ config SMP machine. If you say Y here, U-Boot will run on many, but not all, single processor machines.
+config SPL_SMP + bool "Symmetric Multi-Processing in SPL" + depends on SPL && SPL_RISCV_MMODE + default y + help + This enables support for systems with more than one CPU in SPL. + If you say N here, U-Boot SPL will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor + machine. If you say Y here, U-Boot SPL will run on many, but not + all, single processor machines. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 - depends on SMP + depends on SMP || SPL_SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU. diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ecf0482..fce0982 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -53,7 +53,7 @@ _start: /* mask all interrupts */ csrw MODE_PREFIX(ie), zero
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* check if hart is within range */ /* tp: hart id */ li t0, CONFIG_NR_CPUS @@ -91,7 +91,7 @@ call_board_init_f_0: mv gp, a0
/* setup stack */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, a0, t0 @@ -182,7 +182,7 @@ spl_stack_gd_setup: mv s0, a0
/* setup stack on main hart */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s0, t0 @@ -231,7 +231,7 @@ relocate_code: *Set up the stack */ stack_setup: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s2, t0 @@ -326,7 +326,7 @@ clbss_l: blt t0, t1, clbss_l
relocate_secondary_harts: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* send relocation IPI */ la t0, secondary_hart_relocate add a0, t0, t6 @@ -370,7 +370,7 @@ call_board_init_r: */ jr t4 /* jump to board_init_r() */
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi @@ -393,7 +393,7 @@ secondary_hart_relocate: secondary_hart_loop: wfi
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) csrr t0, MODE_PREFIX(ip) #if CONFIG_IS_ENABLED(RISCV_MMODE) andi t0, t0, MIE_MSIE diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e..72fb4b4 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,7 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index adadbf4..bd7b2c4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -22,7 +22,7 @@ endif obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o
# For building EFI apps diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index ae07bbe..4ca038b 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -41,7 +41,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) invalidate_icache_all();
debug("image entry point: 0x%lX\n", spl_image->entry_point); -#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, 0); if (ret) hang(); diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index a136073..3519c34 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -76,7 +76,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; invalidate_icache_all();
-#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP /* * Start OpenSBI on all secondary harts and wait for acknowledgment. *