On Fri, Dec 02, 2016 at 09:54:39AM +0200, Jyri Sarha wrote:
Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock.
Signed-off-by: Jyri Sarha jsarha@ti.com
[snip]
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 43e122e..c71cfd0 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -25,6 +25,14 @@ #endif #define PHY_EN_DYN_PWRDN (0x1 << 20)
+/**
- AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
- REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
- Synchronization Lost errors.
- */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414 +#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
OK, but the problems I see are that first we don't explain what these values are tied to physically. Is it the display? The DDR memory? Second, since these are board specific they should be in board/ti/am335x/board.h. Thanks!