That's useful to know. The PL180 code is also used for U8500, I don't know if that implements the peripheral ID register; though I guess any probing could be limited to vexpress anyway.
STE have the same "problems" with FIFO size, see drivers/mmc/host/mmci.c in kernel sources:
static struct variant_data variant_arm = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .datalength_bits = 16, };
static struct variant_data variant_arm_extended_fifo = { .fifosize = 128 * 4, .fifohalfsize = 64 * 4, .datalength_bits = 16, };
static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, .datalength_bits = 16, .sdio = true, };
static struct variant_data variant_ux500 = { .fifosize = 30 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, };
static struct variant_data variant_ux500v2 = { .fifosize = 30 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, .datalength_bits = 24, .sdio = true, .st_clkdiv = true, .blksz_datactrl16 = true, };
Cheers!
Paweł