For apollolake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/Kconfig | 5 +++++ arch/x86/dts/u-boot.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 02c116caeb7..9d01801ff13 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -896,4 +896,9 @@ config X86_OFFSET_U_BOOT depends on HAS_SYS_TEXT_BASE default SYS_TEXT_BASE
+config X86_OFFSET_SPL + hex "Offset of SPL in ROM image" + depends on X86 + default SPL_TEXT_BASE + endmenu diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index f33f276b90d..8fc5146f26c 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -49,7 +49,7 @@ u-boot-tpl-dtb { }; u-boot-spl { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-spl-dtb { }; @@ -58,7 +58,7 @@ }; #elif defined(CONFIG_SPL) u-boot-spl-with-ucode-ptr { - offset = <CONFIG_SPL_TEXT_BASE>; + offset = <CONFIG_X86_OFFSET_SPL>; }; u-boot-dtb-with-ucode2 { type = "u-boot-dtb-with-ucode";